89 #define rtsx_pci_writel(pcr, reg, value) \  argument
90 	iowrite32(value, (pcr)->remap_addr + reg)
91 #define rtsx_pci_readl(pcr, reg) \  argument
92 	ioread32((pcr)->remap_addr + reg)
93 #define rtsx_pci_writew(pcr, reg, value) \  argument
94 	iowrite16(value, (pcr)->remap_addr + reg)
95 #define rtsx_pci_readw(pcr, reg) \  argument
96 	ioread16((pcr)->remap_addr + reg)
97 #define rtsx_pci_writeb(pcr, reg, value) \  argument
98 	iowrite8(value, (pcr)->remap_addr + reg)
99 #define rtsx_pci_readb(pcr, reg) \  argument
100 	ioread8((pcr)->remap_addr + reg)
102 #define rtsx_pci_read_config_byte(pcr, where, val) \  argument
103 	pci_read_config_byte((pcr)->pci, where, val)
105 #define rtsx_pci_write_config_byte(pcr, where, val) \  argument
106 	pci_write_config_byte((pcr)->pci, where, val)
108 #define rtsx_pci_read_config_dword(pcr, where, val) \  argument
109 	pci_read_config_dword((pcr)->pci, where, val)
111 #define rtsx_pci_write_config_dword(pcr, where, val) \  argument
112 	pci_write_config_dword((pcr)->pci, where, val)
1052 #define rtsx_pci_init_cmd(pcr)		((pcr)->ci = 0)  argument
1060 	struct rtsx_pcr			*pcr;  member
1064 	int (*write_phy)(struct rtsx_pcr *pcr, u8 addr, u16 val);
1065 	int (*read_phy)(struct rtsx_pcr *pcr, u8 addr, u16 *val);
1066 	int		(*extra_init_hw)(struct rtsx_pcr *pcr);
1067 	int		(*optimize_phy)(struct rtsx_pcr *pcr);
1068 	int		(*turn_on_led)(struct rtsx_pcr *pcr);
1069 	int		(*turn_off_led)(struct rtsx_pcr *pcr);
1070 	int		(*enable_auto_blink)(struct rtsx_pcr *pcr);
1071 	int		(*disable_auto_blink)(struct rtsx_pcr *pcr);
1072 	int		(*card_power_on)(struct rtsx_pcr *pcr, int card);
1073 	int		(*card_power_off)(struct rtsx_pcr *pcr, int card);
1074 	int		(*switch_output_voltage)(struct rtsx_pcr *pcr,
1076 	unsigned int	(*cd_deglitch)(struct rtsx_pcr *pcr);
1078 	void		(*fetch_vendor_settings)(struct rtsx_pcr *pcr);
1079 	void		(*force_power_down)(struct rtsx_pcr *pcr, u8 pm_state);
1080 	void		(*stop_cmd)(struct rtsx_pcr *pcr);
1082 	void (*set_aspm)(struct rtsx_pcr *pcr, bool enable);
1083 	int (*set_ltr_latency)(struct rtsx_pcr *pcr, u32 latency);
1084 	int (*set_l1off_sub)(struct rtsx_pcr *pcr, u8 val);
1085 	void (*set_l1off_cfg_sub_d0)(struct rtsx_pcr *pcr, int active);
1086 	void (*full_on)(struct rtsx_pcr *pcr);
1087 	void (*power_saving)(struct rtsx_pcr *pcr);
1088 	void (*enable_ocp)(struct rtsx_pcr *pcr);
1089 	void (*disable_ocp)(struct rtsx_pcr *pcr);
1090 	void (*init_ocp)(struct rtsx_pcr *pcr);
1091 	void (*process_ocp)(struct rtsx_pcr *pcr);
1092 	int (*get_ocpstat)(struct rtsx_pcr *pcr, u8 *val);
1093 	void (*clear_ocpstat)(struct rtsx_pcr *pcr);
1266 #define CHK_PCI_PID(pcr, pid)		((pcr)->pci->device == (pid))  argument
1267 #define PCI_VID(pcr)			((pcr)->pci->vendor)  argument
1268 #define PCI_PID(pcr)			((pcr)->pci->device)  argument
1269 #define is_version(pcr, pid, ver)				\  argument
1270 	(CHK_PCI_PID(pcr, pid) && (pcr)->ic_version == (ver))
1271 #define pcr_dbg(pcr, fmt, arg...)				\  argument
1272 	dev_dbg(&(pcr)->pci->dev, fmt, ##arg)
1277 #define SDR104_TX_PHASE(pcr)		SDR104_PHASE((pcr)->tx_initial_phase)  argument
1278 #define SDR50_TX_PHASE(pcr)		SDR50_PHASE((pcr)->tx_initial_phase)  argument
1279 #define DDR50_TX_PHASE(pcr)		DDR50_PHASE((pcr)->tx_initial_phase)  argument
1280 #define SDR104_RX_PHASE(pcr)		SDR104_PHASE((pcr)->rx_initial_phase)  argument
1281 #define SDR50_RX_PHASE(pcr)		SDR50_PHASE((pcr)->rx_initial_phase)  argument
1282 #define DDR50_RX_PHASE(pcr)		DDR50_PHASE((pcr)->rx_initial_phase)  argument
1286 void rtsx_pci_start_run(struct rtsx_pcr *pcr);
1287 int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data);
1288 int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data);
1289 int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
1290 int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
1291 void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr);
1292 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
1294 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr);
1295 int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout);
1296 int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1298 int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1300 void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1302 int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1304 int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
1305 int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
1306 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card);
1307 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card);
1308 int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
1310 int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card);
1311 int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card);
1312 int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card);
1313 int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage);
1314 unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr);
1315 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr);
1317 static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr)  in rtsx_pci_get_cmd_data()  argument
1319 	return (u8 *)(pcr->host_cmds_ptr);  in rtsx_pci_get_cmd_data()
1322 static inline int rtsx_pci_update_cfg_byte(struct rtsx_pcr *pcr, int addr,  in rtsx_pci_update_cfg_byte()  argument
1328 	err = pci_read_config_byte(pcr->pci, addr, &val);  in rtsx_pci_update_cfg_byte()
1331 	return pci_write_config_byte(pcr->pci, addr, (val & mask) | append);  in rtsx_pci_update_cfg_byte()
1334 static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val)  in rtsx_pci_write_be32()  argument
1336 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg,     0xFF, val >> 24);  in rtsx_pci_write_be32()
1337 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 1, 0xFF, val >> 16);  in rtsx_pci_write_be32()
1338 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 2, 0xFF, val >> 8);  in rtsx_pci_write_be32()
1339 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 3, 0xFF, val);  in rtsx_pci_write_be32()
1342 static inline int rtsx_pci_update_phy(struct rtsx_pcr *pcr, u8 addr,  in rtsx_pci_update_phy()  argument
1348 	err = rtsx_pci_read_phy_register(pcr, addr, &val);  in rtsx_pci_update_phy()
1352 	return rtsx_pci_write_phy_register(pcr, addr, (val & mask) | append);  in rtsx_pci_update_phy()