89 #define rtsx_pci_writel(pcr, reg, value) \  argument
91 #define rtsx_pci_readl(pcr, reg) \  argument
93 #define rtsx_pci_writew(pcr, reg, value) \  argument
95 #define rtsx_pci_readw(pcr, reg) \  argument
97 #define rtsx_pci_writeb(pcr, reg, value) \  argument
99 #define rtsx_pci_readb(pcr, reg) \  argument
102 #define rtsx_pci_read_config_byte(pcr, where, val) \  argument
105 #define rtsx_pci_write_config_byte(pcr, where, val) \  argument
108 #define rtsx_pci_read_config_dword(pcr, where, val) \  argument
111 #define rtsx_pci_write_config_dword(pcr, where, val) \  argument
1052 #define rtsx_pci_init_cmd(pcr)		((pcr)->ci = 0)  argument
1060 	struct rtsx_pcr			*pcr;  member
1266 #define CHK_PCI_PID(pcr, pid)		((pcr)->pci->device == (pid))  argument
1267 #define PCI_VID(pcr)			((pcr)->pci->vendor)  argument
1268 #define PCI_PID(pcr)			((pcr)->pci->device)  argument
1269 #define is_version(pcr, pid, ver)				\  argument
1271 #define pcr_dbg(pcr, fmt, arg...)				\  argument
1277 #define SDR104_TX_PHASE(pcr)		SDR104_PHASE((pcr)->tx_initial_phase)  argument
1278 #define SDR50_TX_PHASE(pcr)		SDR50_PHASE((pcr)->tx_initial_phase)  argument
1279 #define DDR50_TX_PHASE(pcr)		DDR50_PHASE((pcr)->tx_initial_phase)  argument
1280 #define SDR104_RX_PHASE(pcr)		SDR104_PHASE((pcr)->rx_initial_phase)  argument
1281 #define SDR50_RX_PHASE(pcr)		SDR50_PHASE((pcr)->rx_initial_phase)  argument
1282 #define DDR50_RX_PHASE(pcr)		DDR50_PHASE((pcr)->rx_initial_phase)  argument
1317 static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr)  in rtsx_pci_get_cmd_data()
1322 static inline int rtsx_pci_update_cfg_byte(struct rtsx_pcr *pcr, int addr,  in rtsx_pci_update_cfg_byte()
1334 static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val)  in rtsx_pci_write_be32()
1342 static inline int rtsx_pci_update_phy(struct rtsx_pcr *pcr, u8 addr,  in rtsx_pci_update_phy()