1 /* SPDX-License-Identifier: GPL-2.0-only */
3  *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
8  *	Contains standard defines and IDs for NAND flash devices
20 #include <linux/mtd/nand.h>
28 /* The maximum number of NAND chips in an array */
49  * Standard NAND flash commands
72 #define NAND_CMD_NONE		-1
81 #define NAND_DATA_IFACE_CHECK_ONLY	-1
103  * Constants for Hardware ECC
105 /* Reset Hardware ECC for read */
107 /* Reset Hardware ECC for write */
109 /* Enable Hardware ECC before syndrome is read back from flash */
113  * Enable generic NAND 'page erased' check. This check is only done when
114  * ecc.correct() returns -EBADMSG.
136  * Chip requires ready check on read (for auto-incremented sequential read).
145 /* Device is one of 'new' xD cards that expose fake nand command set */
148 /* Device behaves just like nand, but is readonly */
167 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
190  * Autodetect nand buswidth with readid/onfi.
191  * This suppose the driver will configure the hardware in 8 bits mode
203  * In case your controller is implementing ->legacy.cmd_ctrl() and is relying
204  * on the default ->cmdfunc() implementation, you may want to let the core
213  * Whether the NAND chip is a boot medium. Drivers might use this information
214  * to select ECC algorithms supported by the boot ROM or similar restrictions.
231  * struct nand_parameters - NAND generic parameters from the parameter page
233  * @supports_set_get_features: The NAND chip supports setting/getting features
249 /* The maximum expected count of bytes in the NAND ID sequence */
253  * struct nand_id - NAND id structure
263  * struct nand_ecc_step_info - ECC step information of ECC engine
264  * @stepsize: data bytes per ECC step
275  * struct nand_ecc_caps - capability of ECC engine
276  * @stepinfos: array of ECC step information
277  * @nstepinfos: number of ECC step information
278  * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
286 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
301  * struct nand_ecc_ctrl - Control structure for ECC
302  * @mode:	ECC mode
303  * @algo:	ECC algorithm
304  * @steps:	number of ECC steps per page
305  * @size:	data bytes per ECC step
306  * @bytes:	ECC bytes per step
307  * @strength:	max number of correctible bits per ECC step
308  * @total:	total number of ECC bytes per page
309  * @prepad:	padding information for syndrome based ECC generators
310  * @postpad:	padding information for syndrome based ECC generators
311  * @options:	ECC specific options (see NAND_ECC_XXX flags defined above)
312  * @priv:	pointer to private ECC control data
313  * @calc_buf:	buffer for calculated ECC, size is oobsize.
314  * @code_buf:	buffer for ECC read from flash, size is oobsize.
315  * @hwctl:	function to control hardware ECC generator. Must only
316  *		be provided if an hardware ECC is available
317  * @calculate:	function for ECC calculation or readback from ECC hardware
318  * @correct:	function for ECC correction, matching to ECC generator (sw/hw).
320  *		corrected bitflips, -EBADMSG if the number of bitflips exceed
321  *		ECC strength, or any other error code if the error is not
323  *		If -EBADMSG is returned the input buffers should be left
325  * @read_page_raw:	function to read a raw page without ECC. This function
326  *			should hide the specific layout used by the ECC
327  *			controller and always return contiguous in-band and
328  *			out-of-band data even if they're not stored
329  *			contiguously on the NAND chip (e.g.
330  *			NAND_ECC_HW_SYNDROME interleaves in-band and
331  *			out-of-band data).
332  * @write_page_raw:	function to write a raw page without ECC. This function
333  *			should hide the specific layout used by the ECC
335  *			in-band and out-of-band data. ECC controller is
338  *			NAND_ECC_HW_SYNDROME interleaves in-band and
339  *			out-of-band data).
340  * @read_page:	function to read a page according to the ECC generator
342  *		any single ECC step, -EIO hw error
343  * @read_subpage:	function to read parts of the page covered by ECC;
345  * @write_subpage:	function to write parts of the page covered by ECC.
346  * @write_page:	function to write a page according to the ECC generator
348  * @write_oob_raw:	function to write chip OOB data without ECC
349  * @read_oob_raw:	function to read chip OOB data without ECC
354 	nand_ecc_modes_t mode;  member
367 	void (*hwctl)(struct nand_chip *chip, int mode);
392  * struct nand_sdr_timings - SDR NAND chip timings
394  * This struct defines the timing requirements of a SDR NAND chip.
395  * These information can be found in every NAND datasheets and the timings
413  * @tCHZ_max: CE# high to output hi-Z
422  * @tIR_min: Output hi-Z to RE# low
423  * @tITC_max: Interface and Timing Mode Change time
429  * @tRHZ_max: RE# high to output hi-Z
484  * enum nand_data_interface_type - NAND interface timing type
492  * struct nand_data_interface - NAND interface timing
505  * nand_get_sdr_timings - get SDR timing from data interface
511 	if (conf->type != NAND_SDR_IFACE)  in nand_get_sdr_timings()
512 		return ERR_PTR(-EINVAL);  in nand_get_sdr_timings()
514 	return &conf->timings.sdr;  in nand_get_sdr_timings()
518  * struct nand_op_cmd_instr - Definition of a command instruction
526  * struct nand_op_addr_instr - Definition of an address instruction
536  * struct nand_op_data_instr - Definition of a data instruction
539  * @buf.in: buffer to fill when reading from the NAND chip
540  * @buf.out: buffer to read from when writing to the NAND chip
541  * @force_8bit: force 8-bit access
544  * and are from the controller perspective, so a "in" is a read from the NAND
545  * chip while a "out" is a write to the NAND chip.
557  * struct nand_op_waitrdy_instr - Definition of a wait ready instruction
565  * enum nand_op_instr_type - Definition of all instruction types
581  * struct nand_op_instr - Instruction object
696  * struct nand_subop - a sub operation
700  *			   of the sub-operation
702  *			of the sub-operation
707  * When an operation cannot be handled as is by the NAND controller, it will
708  * be split by the parser into sub-operations which will be passed to the
728  * struct nand_op_parser_addr_constraints - Constraints for address instructions
737  * struct nand_op_parser_data_constraints - Constraints for data instructions
745  * struct nand_op_parser_pattern_elem - One element of a pattern
795  * struct nand_op_parser_pattern - NAND sub-operation pattern descriptor
798  * @exec: the function that will issue a sub-operation
801  * with its constraints. The pattern itself is used by the core to match NAND
802  * chip operation with NAND controller operations.
803  * Once a match between a NAND controller operation pattern and a NAND chip
804  * operation (or a sub-set of a NAND operation) is found, the pattern ->exec()
827  * struct nand_op_parser - NAND controller operation parser descriptor
833  * NAND operation (or tries to determine if a specific operation is supported).
853  * struct nand_operation - NAND operation descriptor
854  * @cs: the CS line to select for this NAND operation
858  * The actual operation structure that will be passed to chip->exec_op().
881 	switch (instr->type) {  in nand_op_trace()
884 			 instr->ctx.cmd.opcode);  in nand_op_trace()
888 			 instr->ctx.addr.naddrs,  in nand_op_trace()
889 			 instr->ctx.addr.naddrs < 64 ?  in nand_op_trace()
890 			 instr->ctx.addr.naddrs : 64,  in nand_op_trace()
891 			 instr->ctx.addr.addrs);  in nand_op_trace()
895 			 instr->ctx.data.len,  in nand_op_trace()
896 			 instr->ctx.data.force_8bit ?  in nand_op_trace()
897 			 ", force 8-bit" : "");  in nand_op_trace()
901 			 instr->ctx.data.len,  in nand_op_trace()
902 			 instr->ctx.data.force_8bit ?  in nand_op_trace()
903 			 ", force 8-bit" : "");  in nand_op_trace()
907 			 instr->ctx.waitrdy.timeout_ms);  in nand_op_trace()
914  * struct nand_controller_ops - Controller operations
916  * @attach_chip: this method is called after the NAND detection phase after
918  *		 size have been set up. ECC requirements are available if
919  *		 provided by the NAND chip or device tree. Typically used to
920  *		 choose the appropriate ECC configuration and allocate
924  *		 nand_controller_ops->attach_chip().
926  * @exec_op:	 controller specific method to execute NAND operations.
927  *		 This method replaces chip->legacy.cmdfunc(),
928  *		 chip->legacy.{read,write}_{buf,byte,word}(),
929  *		 chip->legacy.dev_ready() and chip->legacy.waifunc().
947  * struct nand_controller - Structure used to describe a NAND controller
949  * @lock:		lock used to serialize accesses to the NAND controller
950  * @ops:		NAND controller operations.
959 	mutex_init(&nfc->lock);  in nand_controller_init()
963  * struct nand_legacy - NAND chip legacy fields/hooks
980  * @set_features: set the NAND chip features
981  * @get_features: get the NAND chip features
1014  * struct nand_chip - NAND Private Flash Chip Data
1015  * @base:		Inherit from the generic NAND device
1022  *			setting the read-retry mode. Mostly needed for MLC NAND.
1023  * @ecc:		[BOARDSPECIFIC] ECC control structure
1043  * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
1044  *			      set to the actually used ONFI mode if the chip is
1046  *			      the NAND chip is not ONFI compliant.
1047  * @pagemask:		[INTERN] page number mask = number of (pages / chip) - 1
1051  * @pagecache.page:	Page number currently in the cache. -1 means no page is
1054  * @id:			[INTERN] holds NAND ID
1057  * @data_interface:	[INTERN] NAND interface timing information
1058  * @cur_cs:		currently selected target. -1 means no target selected,
1060  *			cur_cs < nanddev_ntargets(). NAND Controller drivers
1065  *			serialize accesses to the NAND device.
1124 	struct nand_ecc_ctrl ecc;  member
1151 	return &chip->base.mtd;  in nand_to_mtd()
1156 	return chip->priv;  in nand_get_controller_data()
1161 	chip->priv = priv;  in nand_set_controller_data()
1167 	chip->manufacturer.priv = priv;  in nand_set_manufacturer_data()
1172 	return chip->manufacturer.priv;  in nand_get_manufacturer_data()
1187  * A helper for defining older NAND chips where the second ID byte fully
1189  * size). All these chips have 512 bytes NAND page size.
1211 #define NAND_ECC_STRENGTH(type)		((type)->ecc.strength_ds)
1212 #define NAND_ECC_STEP(type)		((type)->ecc.step_ds)
1215  * struct nand_flash_dev - NAND Flash Device ID Structure
1216  * @name: a human-readable name of the NAND chip
1223  * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1224  *            well as the eraseblock size) is determined from the extended NAND
1231  * @ecc: ECC correctability and step information from the datasheet.
1232  * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1234  * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1236  *               For example, the "4bit ECC for each 512Byte" can be set with
1238  * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
1261 	} ecc;  member
1268  * Check if it is a SLC nand.
1269  * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1274 	WARN(nanddev_bits_per_cell(&chip->base) == 0,  in nand_is_slc()
1275 	     "chip->bits_per_cell is used uninitialized\n");  in nand_is_slc()
1276 	return nanddev_bits_per_cell(&chip->base) == 1;  in nand_is_slc()
1298 				void *ecc, int ecclen,
1323 /* Reset and initialize a NAND device */
1326 /* NAND operation helpers */
1354 /* Scan and identify a NAND device */
1367  * Free resources held by the NAND device, must be called on error after a
1383 /* Select/deselect a NAND target. */
1388  * nand_get_data_buf() - Get the internal page buffer
1389  * @chip: NAND chip object
1391  * Returns the pre-allocated page buffer after invalidating the cache. This
1403 	chip->pagecache.page = -1;  in nand_get_data_buf()
1405 	return chip->data_buf;  in nand_get_data_buf()