Lines Matching +full:0 +full:x20
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
80 MLX5_SHARED_RESOURCE_UID = 0xffff,
84 MLX5_OBJ_TYPE_SW_ICM = 0x0008,
93 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
94 MLX5_OBJ_TYPE_MKEY = 0xff01,
95 MLX5_OBJ_TYPE_QP = 0xff02,
96 MLX5_OBJ_TYPE_PSV = 0xff03,
97 MLX5_OBJ_TYPE_RMP = 0xff04,
98 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
99 MLX5_OBJ_TYPE_RQ = 0xff06,
100 MLX5_OBJ_TYPE_SQ = 0xff07,
101 MLX5_OBJ_TYPE_TIR = 0xff08,
102 MLX5_OBJ_TYPE_TIS = 0xff09,
103 MLX5_OBJ_TYPE_DCT = 0xff0a,
104 MLX5_OBJ_TYPE_XRQ = 0xff0b,
105 MLX5_OBJ_TYPE_RQT = 0xff0e,
106 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
107 MLX5_OBJ_TYPE_CQ = 0xff10,
111 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
112 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
113 MLX5_CMD_OP_INIT_HCA = 0x102,
114 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
115 MLX5_CMD_OP_ENABLE_HCA = 0x104,
116 MLX5_CMD_OP_DISABLE_HCA = 0x105,
117 MLX5_CMD_OP_QUERY_PAGES = 0x107,
118 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
119 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
120 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
121 MLX5_CMD_OP_SET_ISSI = 0x10b,
122 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
123 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
124 MLX5_CMD_OP_ALLOC_SF = 0x113,
125 MLX5_CMD_OP_DEALLOC_SF = 0x114,
126 MLX5_CMD_OP_CREATE_MKEY = 0x200,
127 MLX5_CMD_OP_QUERY_MKEY = 0x201,
128 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
129 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
130 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
131 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
132 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
133 MLX5_CMD_OP_CREATE_EQ = 0x301,
134 MLX5_CMD_OP_DESTROY_EQ = 0x302,
135 MLX5_CMD_OP_QUERY_EQ = 0x303,
136 MLX5_CMD_OP_GEN_EQE = 0x304,
137 MLX5_CMD_OP_CREATE_CQ = 0x400,
138 MLX5_CMD_OP_DESTROY_CQ = 0x401,
139 MLX5_CMD_OP_QUERY_CQ = 0x402,
140 MLX5_CMD_OP_MODIFY_CQ = 0x403,
141 MLX5_CMD_OP_CREATE_QP = 0x500,
142 MLX5_CMD_OP_DESTROY_QP = 0x501,
143 MLX5_CMD_OP_RST2INIT_QP = 0x502,
144 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
145 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
146 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
147 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
148 MLX5_CMD_OP_2ERR_QP = 0x507,
149 MLX5_CMD_OP_2RST_QP = 0x50a,
150 MLX5_CMD_OP_QUERY_QP = 0x50b,
151 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
152 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
153 MLX5_CMD_OP_CREATE_PSV = 0x600,
154 MLX5_CMD_OP_DESTROY_PSV = 0x601,
155 MLX5_CMD_OP_CREATE_SRQ = 0x700,
156 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
157 MLX5_CMD_OP_QUERY_SRQ = 0x702,
158 MLX5_CMD_OP_ARM_RQ = 0x703,
159 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
160 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
161 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
162 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
163 MLX5_CMD_OP_CREATE_DCT = 0x710,
164 MLX5_CMD_OP_DESTROY_DCT = 0x711,
165 MLX5_CMD_OP_DRAIN_DCT = 0x712,
166 MLX5_CMD_OP_QUERY_DCT = 0x713,
167 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
168 MLX5_CMD_OP_CREATE_XRQ = 0x717,
169 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
170 MLX5_CMD_OP_QUERY_XRQ = 0x719,
171 MLX5_CMD_OP_ARM_XRQ = 0x71a,
172 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
173 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
174 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
175 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729,
176 MLX5_CMD_OP_MODIFY_XRQ = 0x72a,
177 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
178 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
179 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
180 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
181 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
182 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
183 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
184 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
185 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
186 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
187 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
188 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
189 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
190 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
191 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
192 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
193 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
194 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
195 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
196 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
197 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
198 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
199 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
200 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
201 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
202 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
203 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
204 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
205 MLX5_CMD_OP_ALLOC_PD = 0x800,
206 MLX5_CMD_OP_DEALLOC_PD = 0x801,
207 MLX5_CMD_OP_ALLOC_UAR = 0x802,
208 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
209 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
210 MLX5_CMD_OP_ACCESS_REG = 0x805,
211 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
212 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
213 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
214 MLX5_CMD_OP_MAD_IFC = 0x50d,
215 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
216 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
217 MLX5_CMD_OP_NOP = 0x80d,
218 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
219 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
220 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
221 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
222 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
223 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
224 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
225 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
226 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
227 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
228 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
229 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
230 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
231 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
232 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
233 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
234 MLX5_CMD_OP_CREATE_LAG = 0x840,
235 MLX5_CMD_OP_MODIFY_LAG = 0x841,
236 MLX5_CMD_OP_QUERY_LAG = 0x842,
237 MLX5_CMD_OP_DESTROY_LAG = 0x843,
238 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
239 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
240 MLX5_CMD_OP_CREATE_TIR = 0x900,
241 MLX5_CMD_OP_MODIFY_TIR = 0x901,
242 MLX5_CMD_OP_DESTROY_TIR = 0x902,
243 MLX5_CMD_OP_QUERY_TIR = 0x903,
244 MLX5_CMD_OP_CREATE_SQ = 0x904,
245 MLX5_CMD_OP_MODIFY_SQ = 0x905,
246 MLX5_CMD_OP_DESTROY_SQ = 0x906,
247 MLX5_CMD_OP_QUERY_SQ = 0x907,
248 MLX5_CMD_OP_CREATE_RQ = 0x908,
249 MLX5_CMD_OP_MODIFY_RQ = 0x909,
250 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
251 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
252 MLX5_CMD_OP_QUERY_RQ = 0x90b,
253 MLX5_CMD_OP_CREATE_RMP = 0x90c,
254 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
255 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
256 MLX5_CMD_OP_QUERY_RMP = 0x90f,
257 MLX5_CMD_OP_CREATE_TIS = 0x912,
258 MLX5_CMD_OP_MODIFY_TIS = 0x913,
259 MLX5_CMD_OP_DESTROY_TIS = 0x914,
260 MLX5_CMD_OP_QUERY_TIS = 0x915,
261 MLX5_CMD_OP_CREATE_RQT = 0x916,
262 MLX5_CMD_OP_MODIFY_RQT = 0x917,
263 MLX5_CMD_OP_DESTROY_RQT = 0x918,
264 MLX5_CMD_OP_QUERY_RQT = 0x919,
265 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
266 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
267 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
268 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
269 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
270 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
271 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
272 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
273 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
274 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
275 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
276 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
277 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
278 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
279 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
280 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
281 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
282 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
283 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
284 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
285 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
286 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
287 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
288 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
289 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
290 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
291 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
292 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
293 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
294 MLX5_CMD_OP_CREATE_UCTX = 0xa04,
295 MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
296 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
297 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
298 MLX5_CMD_OP_SYNC_STEERING = 0xb00,
304 MLX5_CMD_OP_GENERAL_START = 0xb00,
305 MLX5_CMD_OP_GENERAL_END = 0xd00,
309 u8 outer_dmac[0x1];
310 u8 outer_smac[0x1];
311 u8 outer_ether_type[0x1];
312 u8 outer_ip_version[0x1];
313 u8 outer_first_prio[0x1];
314 u8 outer_first_cfi[0x1];
315 u8 outer_first_vid[0x1];
316 u8 outer_ipv4_ttl[0x1];
317 u8 outer_second_prio[0x1];
318 u8 outer_second_cfi[0x1];
319 u8 outer_second_vid[0x1];
320 u8 reserved_at_b[0x1];
321 u8 outer_sip[0x1];
322 u8 outer_dip[0x1];
323 u8 outer_frag[0x1];
324 u8 outer_ip_protocol[0x1];
325 u8 outer_ip_ecn[0x1];
326 u8 outer_ip_dscp[0x1];
327 u8 outer_udp_sport[0x1];
328 u8 outer_udp_dport[0x1];
329 u8 outer_tcp_sport[0x1];
330 u8 outer_tcp_dport[0x1];
331 u8 outer_tcp_flags[0x1];
332 u8 outer_gre_protocol[0x1];
333 u8 outer_gre_key[0x1];
334 u8 outer_vxlan_vni[0x1];
335 u8 outer_geneve_vni[0x1];
336 u8 outer_geneve_oam[0x1];
337 u8 outer_geneve_protocol_type[0x1];
338 u8 outer_geneve_opt_len[0x1];
339 u8 reserved_at_1e[0x1];
340 u8 source_eswitch_port[0x1];
342 u8 inner_dmac[0x1];
343 u8 inner_smac[0x1];
344 u8 inner_ether_type[0x1];
345 u8 inner_ip_version[0x1];
346 u8 inner_first_prio[0x1];
347 u8 inner_first_cfi[0x1];
348 u8 inner_first_vid[0x1];
349 u8 reserved_at_27[0x1];
350 u8 inner_second_prio[0x1];
351 u8 inner_second_cfi[0x1];
352 u8 inner_second_vid[0x1];
353 u8 reserved_at_2b[0x1];
354 u8 inner_sip[0x1];
355 u8 inner_dip[0x1];
356 u8 inner_frag[0x1];
357 u8 inner_ip_protocol[0x1];
358 u8 inner_ip_ecn[0x1];
359 u8 inner_ip_dscp[0x1];
360 u8 inner_udp_sport[0x1];
361 u8 inner_udp_dport[0x1];
362 u8 inner_tcp_sport[0x1];
363 u8 inner_tcp_dport[0x1];
364 u8 inner_tcp_flags[0x1];
365 u8 reserved_at_37[0x9];
367 u8 geneve_tlv_option_0_data[0x1];
368 u8 reserved_at_41[0x4];
369 u8 outer_first_mpls_over_udp[0x4];
370 u8 outer_first_mpls_over_gre[0x4];
371 u8 inner_first_mpls[0x4];
372 u8 outer_first_mpls[0x4];
373 u8 reserved_at_55[0x2];
374 u8 outer_esp_spi[0x1];
375 u8 reserved_at_58[0x2];
376 u8 bth_dst_qp[0x1];
378 u8 reserved_at_5b[0x25];
382 u8 ft_support[0x1];
383 u8 reserved_at_1[0x1];
384 u8 flow_counter[0x1];
385 u8 flow_modify_en[0x1];
386 u8 modify_root[0x1];
387 u8 identified_miss_table_mode[0x1];
388 u8 flow_table_modify[0x1];
389 u8 reformat[0x1];
390 u8 decap[0x1];
391 u8 reserved_at_9[0x1];
392 u8 pop_vlan[0x1];
393 u8 push_vlan[0x1];
394 u8 reserved_at_c[0x1];
395 u8 pop_vlan_2[0x1];
396 u8 push_vlan_2[0x1];
397 u8 reformat_and_vlan_action[0x1];
398 u8 reserved_at_10[0x1];
399 u8 sw_owner[0x1];
400 u8 reformat_l3_tunnel_to_l2[0x1];
401 u8 reformat_l2_to_l3_tunnel[0x1];
402 u8 reformat_and_modify_action[0x1];
403 u8 reserved_at_15[0x2];
404 u8 table_miss_action_domain[0x1];
405 u8 termination_table[0x1];
406 u8 reserved_at_19[0x7];
407 u8 reserved_at_20[0x2];
408 u8 log_max_ft_size[0x6];
409 u8 log_max_modify_header_context[0x8];
410 u8 max_modify_header_actions[0x8];
411 u8 max_ft_level[0x8];
413 u8 reserved_at_40[0x20];
415 u8 reserved_at_60[0x18];
416 u8 log_max_ft_num[0x8];
418 u8 reserved_at_80[0x18];
419 u8 log_max_destination[0x8];
421 u8 log_max_flow_counter[0x8];
422 u8 reserved_at_a8[0x10];
423 u8 log_max_flow[0x8];
425 u8 reserved_at_c0[0x40];
433 u8 send[0x1];
434 u8 receive[0x1];
435 u8 write[0x1];
436 u8 read[0x1];
437 u8 atomic[0x1];
438 u8 srq_receive[0x1];
439 u8 reserved_at_6[0x1a];
443 u8 smac_47_16[0x20];
445 u8 smac_15_0[0x10];
446 u8 ethertype[0x10];
448 u8 dmac_47_16[0x20];
450 u8 dmac_15_0[0x10];
451 u8 first_prio[0x3];
452 u8 first_cfi[0x1];
453 u8 first_vid[0xc];
455 u8 ip_protocol[0x8];
456 u8 ip_dscp[0x6];
457 u8 ip_ecn[0x2];
458 u8 cvlan_tag[0x1];
459 u8 svlan_tag[0x1];
460 u8 frag[0x1];
461 u8 ip_version[0x4];
462 u8 tcp_flags[0x9];
464 u8 tcp_sport[0x10];
465 u8 tcp_dport[0x10];
467 u8 reserved_at_c0[0x18];
468 u8 ttl_hoplimit[0x8];
470 u8 udp_sport[0x10];
471 u8 udp_dport[0x10];
479 u8 hi[0x18];
480 u8 lo[0x8];
485 u8 key[0x20];
489 u8 gre_c_present[0x1];
490 u8 reserved_at_1[0x1];
491 u8 gre_k_present[0x1];
492 u8 gre_s_present[0x1];
493 u8 source_vhca_port[0x4];
494 u8 source_sqn[0x18];
496 u8 source_eswitch_owner_vhca_id[0x10];
497 u8 source_port[0x10];
499 u8 outer_second_prio[0x3];
500 u8 outer_second_cfi[0x1];
501 u8 outer_second_vid[0xc];
502 u8 inner_second_prio[0x3];
503 u8 inner_second_cfi[0x1];
504 u8 inner_second_vid[0xc];
506 u8 outer_second_cvlan_tag[0x1];
507 u8 inner_second_cvlan_tag[0x1];
508 u8 outer_second_svlan_tag[0x1];
509 u8 inner_second_svlan_tag[0x1];
510 u8 reserved_at_64[0xc];
511 u8 gre_protocol[0x10];
515 u8 vxlan_vni[0x18];
516 u8 reserved_at_b8[0x8];
518 u8 geneve_vni[0x18];
519 u8 reserved_at_d8[0x7];
520 u8 geneve_oam[0x1];
522 u8 reserved_at_e0[0xc];
523 u8 outer_ipv6_flow_label[0x14];
525 u8 reserved_at_100[0xc];
526 u8 inner_ipv6_flow_label[0x14];
528 u8 reserved_at_120[0xa];
529 u8 geneve_opt_len[0x6];
530 u8 geneve_protocol_type[0x10];
532 u8 reserved_at_140[0x8];
533 u8 bth_dst_qp[0x18];
534 u8 reserved_at_160[0x20];
535 u8 outer_esp_spi[0x20];
536 u8 reserved_at_1a0[0x60];
540 u8 mpls_label[0x14];
541 u8 mpls_exp[0x3];
542 u8 mpls_s_bos[0x1];
543 u8 mpls_ttl[0x8];
555 u8 metadata_reg_c_7[0x20];
557 u8 metadata_reg_c_6[0x20];
559 u8 metadata_reg_c_5[0x20];
561 u8 metadata_reg_c_4[0x20];
563 u8 metadata_reg_c_3[0x20];
565 u8 metadata_reg_c_2[0x20];
567 u8 metadata_reg_c_1[0x20];
569 u8 metadata_reg_c_0[0x20];
571 u8 metadata_reg_a[0x20];
573 u8 metadata_reg_b[0x20];
575 u8 reserved_at_1c0[0x40];
579 u8 inner_tcp_seq_num[0x20];
581 u8 outer_tcp_seq_num[0x20];
583 u8 inner_tcp_ack_num[0x20];
585 u8 outer_tcp_ack_num[0x20];
587 u8 reserved_at_80[0x8];
588 u8 outer_vxlan_gpe_vni[0x18];
590 u8 outer_vxlan_gpe_next_protocol[0x8];
591 u8 outer_vxlan_gpe_flags[0x8];
592 u8 reserved_at_b0[0x10];
594 u8 icmp_header_data[0x20];
596 u8 icmpv6_header_data[0x20];
598 u8 icmp_type[0x8];
599 u8 icmp_code[0x8];
600 u8 icmpv6_type[0x8];
601 u8 icmpv6_code[0x8];
603 u8 geneve_tlv_option_0_data[0x20];
605 u8 reserved_at_140[0xc0];
609 u8 pa_h[0x20];
611 u8 pa_l[0x14];
612 u8 reserved_at_34[0xc];
616 u8 hi[0x20];
618 u8 lo[0x20];
622 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
623 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
624 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
625 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
626 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
627 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
628 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
629 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
630 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
631 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
635 u8 fl[0x1];
636 u8 free_ar[0x1];
637 u8 reserved_at_2[0xe];
638 u8 pkey_index[0x10];
640 u8 reserved_at_20[0x8];
641 u8 grh[0x1];
642 u8 mlid[0x7];
643 u8 rlid[0x10];
645 u8 ack_timeout[0x5];
646 u8 reserved_at_45[0x3];
647 u8 src_addr_index[0x8];
648 u8 reserved_at_50[0x4];
649 u8 stat_rate[0x4];
650 u8 hop_limit[0x8];
652 u8 reserved_at_60[0x4];
653 u8 tclass[0x8];
654 u8 flow_label[0x14];
656 u8 rgid_rip[16][0x8];
658 u8 reserved_at_100[0x4];
659 u8 f_dscp[0x1];
660 u8 f_ecn[0x1];
661 u8 reserved_at_106[0x1];
662 u8 f_eth_prio[0x1];
663 u8 ecn[0x2];
664 u8 dscp[0x6];
665 u8 udp_sport[0x10];
667 u8 dei_cfi[0x1];
668 u8 eth_prio[0x3];
669 u8 sl[0x4];
670 u8 vhca_port_num[0x8];
671 u8 rmac_47_32[0x10];
673 u8 rmac_31_0[0x20];
677 u8 nic_rx_multi_path_tirs[0x1];
678 u8 nic_rx_multi_path_tirs_fts[0x1];
679 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
680 u8 reserved_at_3[0x1d];
681 u8 encap_general_header[0x1];
682 u8 reserved_at_21[0xa];
683 u8 log_max_packet_reformat_context[0x5];
684 u8 reserved_at_30[0x6];
685 u8 max_encap_header_size[0xa];
686 u8 reserved_at_40[0x1c0];
696 u8 reserved_at_a00[0x200];
700 u8 reserved_at_e00[0x1200];
702 u8 sw_steering_nic_rx_action_drop_icm_address[0x40];
704 u8 sw_steering_nic_tx_action_drop_icm_address[0x40];
706 u8 sw_steering_nic_tx_action_allow_icm_address[0x40];
708 u8 reserved_at_20c0[0x5f40];
712 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
713 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
714 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
715 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
716 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
717 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
718 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
719 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
723 u8 fdb_to_vport_reg_c_id[0x8];
724 u8 reserved_at_8[0xf];
725 u8 flow_source[0x1];
726 u8 reserved_at_18[0x2];
727 u8 multi_fdb_encap[0x1];
728 u8 reserved_at_1b[0x1];
729 u8 fdb_multi_path_to_table[0x1];
730 u8 reserved_at_1d[0x3];
732 u8 reserved_at_20[0x1e0];
740 u8 reserved_at_800[0x1000];
742 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40];
744 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40];
746 u8 sw_steering_uplink_icm_address_rx[0x40];
748 u8 sw_steering_uplink_icm_address_tx[0x40];
750 u8 reserved_at_1900[0x6700];
754 MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
755 MLX5_COUNTER_FLOW_ESWITCH = 0x1,
759 u8 vport_svlan_strip[0x1];
760 u8 vport_cvlan_strip[0x1];
761 u8 vport_svlan_insert[0x1];
762 u8 vport_cvlan_insert_if_not_exist[0x1];
763 u8 vport_cvlan_insert_overwrite[0x1];
764 u8 reserved_at_5[0x3];
765 u8 esw_uplink_ingress_acl[0x1];
766 u8 reserved_at_9[0x10];
767 u8 esw_functions_changed[0x1];
768 u8 reserved_at_1a[0x1];
769 u8 ecpf_vport_exists[0x1];
770 u8 counter_eswitch_affinity[0x1];
771 u8 merged_eswitch[0x1];
772 u8 nic_vport_node_guid_modify[0x1];
773 u8 nic_vport_port_guid_modify[0x1];
775 u8 vxlan_encap_decap[0x1];
776 u8 nvgre_encap_decap[0x1];
777 u8 reserved_at_22[0x1];
778 u8 log_max_fdb_encap_uplink[0x5];
779 u8 reserved_at_21[0x3];
780 u8 log_max_packet_reformat_context[0x5];
781 u8 reserved_2b[0x6];
782 u8 max_encap_header_size[0xa];
784 u8 reserved_at_40[0xb];
785 u8 log_max_esw_sf[0x5];
786 u8 esw_sf_base_id[0x10];
788 u8 reserved_at_60[0x7a0];
793 u8 packet_pacing[0x1];
794 u8 esw_scheduling[0x1];
795 u8 esw_bw_share[0x1];
796 u8 esw_rate_limit[0x1];
797 u8 reserved_at_4[0x1];
798 u8 packet_pacing_burst_bound[0x1];
799 u8 packet_pacing_typical_size[0x1];
800 u8 reserved_at_7[0x19];
802 u8 reserved_at_20[0x20];
804 u8 packet_pacing_max_rate[0x20];
806 u8 packet_pacing_min_rate[0x20];
808 u8 reserved_at_80[0x10];
809 u8 packet_pacing_rate_table_size[0x10];
811 u8 esw_element_type[0x10];
812 u8 esw_tsar_type[0x10];
814 u8 reserved_at_c0[0x10];
815 u8 max_qos_para_vport[0x10];
817 u8 max_tsar_bw_share[0x20];
819 u8 reserved_at_100[0x700];
823 u8 core_dump_general[0x1];
824 u8 core_dump_qp[0x1];
825 u8 reserved_at_2[0x1e];
827 u8 reserved_at_20[0x2];
828 u8 stall_detect[0x1];
829 u8 reserved_at_23[0x1d];
831 u8 reserved_at_40[0x7c0];
835 u8 csum_cap[0x1];
836 u8 vlan_cap[0x1];
837 u8 lro_cap[0x1];
838 u8 lro_psh_flag[0x1];
839 u8 lro_time_stamp[0x1];
840 u8 reserved_at_5[0x2];
841 u8 wqe_vlan_insert[0x1];
842 u8 self_lb_en_modifiable[0x1];
843 u8 reserved_at_9[0x2];
844 u8 max_lso_cap[0x5];
845 u8 multi_pkt_send_wqe[0x2];
846 u8 wqe_inline_mode[0x2];
847 u8 rss_ind_tbl_cap[0x4];
848 u8 reg_umr_sq[0x1];
849 u8 scatter_fcs[0x1];
850 u8 enhanced_multi_pkt_send_wqe[0x1];
851 u8 tunnel_lso_const_out_ip_id[0x1];
852 u8 reserved_at_1c[0x2];
853 u8 tunnel_stateless_gre[0x1];
854 u8 tunnel_stateless_vxlan[0x1];
856 u8 swp[0x1];
857 u8 swp_csum[0x1];
858 u8 swp_lso[0x1];
859 u8 cqe_checksum_full[0x1];
860 u8 reserved_at_24[0x5];
861 u8 tunnel_stateless_ip_over_ip[0x1];
862 u8 reserved_at_2a[0x6];
863 u8 max_vxlan_udp_ports[0x8];
864 u8 reserved_at_38[0x6];
865 u8 max_geneve_opt_len[0x1];
866 u8 tunnel_stateless_geneve_rx[0x1];
868 u8 reserved_at_40[0x10];
869 u8 lro_min_mss_size[0x10];
871 u8 reserved_at_60[0x120];
873 u8 lro_timer_supported_periods[4][0x20];
875 u8 reserved_at_200[0x600];
879 u8 roce_apm[0x1];
880 u8 reserved_at_1[0x1f];
882 u8 reserved_at_20[0x60];
884 u8 reserved_at_80[0xc];
885 u8 l3_type[0x4];
886 u8 reserved_at_90[0x8];
887 u8 roce_version[0x8];
889 u8 reserved_at_a0[0x10];
890 u8 r_roce_dest_udp_port[0x10];
892 u8 r_roce_max_src_udp_port[0x10];
893 u8 r_roce_min_src_udp_port[0x10];
895 u8 reserved_at_e0[0x10];
896 u8 roce_address_table_size[0x10];
898 u8 reserved_at_100[0x700];
902 u8 opcode[0x10];
903 u8 uid[0x10];
905 u8 reserved_at_20[0x10];
906 u8 op_mod[0x10];
908 u8 reserved_at_40[0xc0];
912 u8 status[0x8];
913 u8 reserved_at_8[0x18];
915 u8 syndrome[0x20];
917 u8 reserved_at_40[0x40];
921 u8 memic[0x1];
922 u8 reserved_at_1[0x1f];
924 u8 reserved_at_20[0xb];
925 u8 log_min_memic_alloc_size[0x5];
926 u8 reserved_at_30[0x8];
927 u8 log_max_memic_addr_alignment[0x8];
929 u8 memic_bar_start_addr[0x40];
931 u8 memic_bar_size[0x20];
933 u8 max_memic_size[0x20];
935 u8 steering_sw_icm_start_address[0x40];
937 u8 reserved_at_100[0x8];
938 u8 log_header_modify_sw_icm_size[0x8];
939 u8 reserved_at_110[0x2];
940 u8 log_sw_icm_alloc_granularity[0x6];
941 u8 log_steering_sw_icm_size[0x8];
943 u8 reserved_at_120[0x20];
945 u8 header_modify_sw_icm_start_address[0x40];
947 u8 reserved_at_180[0x680];
951 u8 user_affiliated_events[4][0x40];
953 u8 user_unaffiliated_events[4][0x40];
957 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
958 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
959 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
960 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
961 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
962 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
963 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
964 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
965 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
969 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
970 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
971 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
972 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
973 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
974 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
975 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
976 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
977 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
981 u8 reserved_at_0[0x40];
983 u8 atomic_req_8B_endianness_mode[0x2];
984 u8 reserved_at_42[0x4];
985 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
987 u8 reserved_at_47[0x19];
989 u8 reserved_at_60[0x20];
991 u8 reserved_at_80[0x10];
992 u8 atomic_operations[0x10];
994 u8 reserved_at_a0[0x10];
995 u8 atomic_size_qp[0x10];
997 u8 reserved_at_c0[0x10];
998 u8 atomic_size_dc[0x10];
1000 u8 reserved_at_e0[0x720];
1004 u8 reserved_at_0[0x40];
1006 u8 sig[0x1];
1007 u8 reserved_at_41[0x1f];
1009 u8 reserved_at_60[0x20];
1021 u8 reserved_at_120[0x6E0];
1025 u8 reserved_at_0[0x10];
1026 u8 reserved_at_10[0x9];
1027 u8 op_swap_endianness[0x1];
1028 u8 op_min[0x1];
1029 u8 op_xor[0x1];
1030 u8 op_or[0x1];
1031 u8 op_and[0x1];
1032 u8 op_max[0x1];
1033 u8 op_add[0x1];
1037 u8 calc_matrix[0x1];
1038 u8 reserved_at_1[0x1f];
1039 u8 reserved_at_20[0x8];
1040 u8 max_vec_count[0x8];
1041 u8 reserved_at_30[0xd];
1042 u8 max_chunk_size[0x3];
1048 u8 reserved_at_c0[0x720];
1052 u8 tls_1_2_aes_gcm_128[0x1];
1053 u8 tls_1_3_aes_gcm_128[0x1];
1054 u8 tls_1_2_aes_gcm_256[0x1];
1055 u8 tls_1_3_aes_gcm_256[0x1];
1056 u8 reserved_at_4[0x1c];
1058 u8 reserved_at_20[0x7e0];
1062 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1063 MLX5_WQ_TYPE_CYCLIC = 0x1,
1064 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1065 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1069 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1070 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1074 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1075 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1076 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1077 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1078 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1082 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1083 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1084 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1085 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1086 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1087 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1091 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1092 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1096 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1097 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1098 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1102 MLX5_CAP_PORT_TYPE_IB = 0x0,
1103 MLX5_CAP_PORT_TYPE_ETH = 0x1,
1107 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
1108 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
1109 MLX5_CAP_UMR_FENCE_NONE = 0x2,
1119 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1126 MLX5_FC_BULK_128 = (1 << 0),
1139 u8 reserved_at_0[0x30];
1140 u8 vhca_id[0x10];
1142 u8 reserved_at_40[0x40];
1144 u8 log_max_srq_sz[0x8];
1145 u8 log_max_qp_sz[0x8];
1146 u8 event_cap[0x1];
1147 u8 reserved_at_91[0x7];
1148 u8 prio_tag_required[0x1];
1149 u8 reserved_at_99[0x2];
1150 u8 log_max_qp[0x5];
1152 u8 reserved_at_a0[0xb];
1153 u8 log_max_srq[0x5];
1154 u8 reserved_at_b0[0x10];
1156 u8 reserved_at_c0[0x8];
1157 u8 log_max_cq_sz[0x8];
1158 u8 reserved_at_d0[0xb];
1159 u8 log_max_cq[0x5];
1161 u8 log_max_eq_sz[0x8];
1162 u8 reserved_at_e8[0x2];
1163 u8 log_max_mkey[0x6];
1164 u8 reserved_at_f0[0x8];
1165 u8 dump_fill_mkey[0x1];
1166 u8 reserved_at_f9[0x2];
1167 u8 fast_teardown[0x1];
1168 u8 log_max_eq[0x4];
1170 u8 max_indirection[0x8];
1171 u8 fixed_buffer_size[0x1];
1172 u8 log_max_mrw_sz[0x7];
1173 u8 force_teardown[0x1];
1174 u8 reserved_at_111[0x1];
1175 u8 log_max_bsf_list_size[0x6];
1176 u8 umr_extended_translation_offset[0x1];
1177 u8 null_mkey[0x1];
1178 u8 log_max_klm_list_size[0x6];
1180 u8 reserved_at_120[0xa];
1181 u8 log_max_ra_req_dc[0x6];
1182 u8 reserved_at_130[0xa];
1183 u8 log_max_ra_res_dc[0x6];
1185 u8 reserved_at_140[0xa];
1186 u8 log_max_ra_req_qp[0x6];
1187 u8 reserved_at_150[0xa];
1188 u8 log_max_ra_res_qp[0x6];
1190 u8 end_pad[0x1];
1191 u8 cc_query_allowed[0x1];
1192 u8 cc_modify_allowed[0x1];
1193 u8 start_pad[0x1];
1194 u8 cache_line_128byte[0x1];
1195 u8 reserved_at_165[0x4];
1196 u8 rts2rts_qp_counters_set_id[0x1];
1197 u8 reserved_at_16a[0x2];
1198 u8 vnic_env_int_rq_oob[0x1];
1199 u8 sbcam_reg[0x1];
1200 u8 reserved_at_16e[0x1];
1201 u8 qcam_reg[0x1];
1202 u8 gid_table_size[0x10];
1204 u8 out_of_seq_cnt[0x1];
1205 u8 vport_counters[0x1];
1206 u8 retransmission_q_counters[0x1];
1207 u8 debug[0x1];
1208 u8 modify_rq_counter_set_id[0x1];
1209 u8 rq_delay_drop[0x1];
1210 u8 max_qp_cnt[0xa];
1211 u8 pkey_table_size[0x10];
1213 u8 vport_group_manager[0x1];
1214 u8 vhca_group_manager[0x1];
1215 u8 ib_virt[0x1];
1216 u8 eth_virt[0x1];
1217 u8 vnic_env_queue_counters[0x1];
1218 u8 ets[0x1];
1219 u8 nic_flow_table[0x1];
1220 u8 eswitch_manager[0x1];
1221 u8 device_memory[0x1];
1222 u8 mcam_reg[0x1];
1223 u8 pcam_reg[0x1];
1224 u8 local_ca_ack_delay[0x5];
1225 u8 port_module_event[0x1];
1226 u8 enhanced_error_q_counters[0x1];
1227 u8 ports_check[0x1];
1228 u8 reserved_at_1b3[0x1];
1229 u8 disable_link_up[0x1];
1230 u8 beacon_led[0x1];
1231 u8 port_type[0x2];
1232 u8 num_ports[0x8];
1234 u8 reserved_at_1c0[0x1];
1235 u8 pps[0x1];
1236 u8 pps_modify[0x1];
1237 u8 log_max_msg[0x5];
1238 u8 reserved_at_1c8[0x4];
1239 u8 max_tc[0x4];
1240 u8 temp_warn_event[0x1];
1241 u8 dcbx[0x1];
1242 u8 general_notification_event[0x1];
1243 u8 reserved_at_1d3[0x2];
1244 u8 fpga[0x1];
1245 u8 rol_s[0x1];
1246 u8 rol_g[0x1];
1247 u8 reserved_at_1d8[0x1];
1248 u8 wol_s[0x1];
1249 u8 wol_g[0x1];
1250 u8 wol_a[0x1];
1251 u8 wol_b[0x1];
1252 u8 wol_m[0x1];
1253 u8 wol_u[0x1];
1254 u8 wol_p[0x1];
1256 u8 stat_rate_support[0x10];
1257 u8 reserved_at_1f0[0xc];
1258 u8 cqe_version[0x4];
1260 u8 compact_address_vector[0x1];
1261 u8 striding_rq[0x1];
1262 u8 reserved_at_202[0x1];
1263 u8 ipoib_enhanced_offloads[0x1];
1264 u8 ipoib_basic_offloads[0x1];
1265 u8 reserved_at_205[0x1];
1266 u8 repeated_block_disabled[0x1];
1267 u8 umr_modify_entity_size_disabled[0x1];
1268 u8 umr_modify_atomic_disabled[0x1];
1269 u8 umr_indirect_mkey_disabled[0x1];
1270 u8 umr_fence[0x2];
1271 u8 dc_req_scat_data_cqe[0x1];
1272 u8 reserved_at_20d[0x2];
1273 u8 drain_sigerr[0x1];
1274 u8 cmdif_checksum[0x2];
1275 u8 sigerr_cqe[0x1];
1276 u8 reserved_at_213[0x1];
1277 u8 wq_signature[0x1];
1278 u8 sctr_data_cqe[0x1];
1279 u8 reserved_at_216[0x1];
1280 u8 sho[0x1];
1281 u8 tph[0x1];
1282 u8 rf[0x1];
1283 u8 dct[0x1];
1284 u8 qos[0x1];
1285 u8 eth_net_offloads[0x1];
1286 u8 roce[0x1];
1287 u8 atomic[0x1];
1288 u8 reserved_at_21f[0x1];
1290 u8 cq_oi[0x1];
1291 u8 cq_resize[0x1];
1292 u8 cq_moderation[0x1];
1293 u8 reserved_at_223[0x3];
1294 u8 cq_eq_remap[0x1];
1295 u8 pg[0x1];
1296 u8 block_lb_mc[0x1];
1297 u8 reserved_at_229[0x1];
1298 u8 scqe_break_moderation[0x1];
1299 u8 cq_period_start_from_cqe[0x1];
1300 u8 cd[0x1];
1301 u8 reserved_at_22d[0x1];
1302 u8 apm[0x1];
1303 u8 vector_calc[0x1];
1304 u8 umr_ptr_rlky[0x1];
1305 u8 imaicl[0x1];
1306 u8 qp_packet_based[0x1];
1307 u8 reserved_at_233[0x3];
1308 u8 qkv[0x1];
1309 u8 pkv[0x1];
1310 u8 set_deth_sqpn[0x1];
1311 u8 reserved_at_239[0x3];
1312 u8 xrc[0x1];
1313 u8 ud[0x1];
1314 u8 uc[0x1];
1315 u8 rc[0x1];
1317 u8 uar_4k[0x1];
1318 u8 reserved_at_241[0x9];
1319 u8 uar_sz[0x6];
1320 u8 reserved_at_250[0x8];
1321 u8 log_pg_sz[0x8];
1323 u8 bf[0x1];
1324 u8 driver_version[0x1];
1325 u8 pad_tx_eth_packet[0x1];
1326 u8 reserved_at_263[0x8];
1327 u8 log_bf_reg_size[0x5];
1329 u8 reserved_at_270[0x8];
1330 u8 lag_tx_port_affinity[0x1];
1331 u8 reserved_at_279[0x2];
1332 u8 lag_master[0x1];
1333 u8 num_lag_ports[0x4];
1335 u8 reserved_at_280[0x10];
1336 u8 max_wqe_sz_sq[0x10];
1338 u8 reserved_at_2a0[0x10];
1339 u8 max_wqe_sz_rq[0x10];
1341 u8 max_flow_counter_31_16[0x10];
1342 u8 max_wqe_sz_sq_dc[0x10];
1344 u8 reserved_at_2e0[0x7];
1345 u8 max_qp_mcg[0x19];
1347 u8 reserved_at_300[0x10];
1348 u8 flow_counter_bulk_alloc[0x8];
1349 u8 log_max_mcg[0x8];
1351 u8 reserved_at_320[0x3];
1352 u8 log_max_transport_domain[0x5];
1353 u8 reserved_at_328[0x3];
1354 u8 log_max_pd[0x5];
1355 u8 reserved_at_330[0xb];
1356 u8 log_max_xrcd[0x5];
1358 u8 nic_receive_steering_discard[0x1];
1359 u8 receive_discard_vport_down[0x1];
1360 u8 transmit_discard_vport_down[0x1];
1361 u8 reserved_at_343[0x5];
1362 u8 log_max_flow_counter_bulk[0x8];
1363 u8 max_flow_counter_15_0[0x10];
1366 u8 reserved_at_360[0x3];
1367 u8 log_max_rq[0x5];
1368 u8 reserved_at_368[0x3];
1369 u8 log_max_sq[0x5];
1370 u8 reserved_at_370[0x3];
1371 u8 log_max_tir[0x5];
1372 u8 reserved_at_378[0x3];
1373 u8 log_max_tis[0x5];
1375 u8 basic_cyclic_rcv_wqe[0x1];
1376 u8 reserved_at_381[0x2];
1377 u8 log_max_rmp[0x5];
1378 u8 reserved_at_388[0x3];
1379 u8 log_max_rqt[0x5];
1380 u8 reserved_at_390[0x3];
1381 u8 log_max_rqt_size[0x5];
1382 u8 reserved_at_398[0x3];
1383 u8 log_max_tis_per_sq[0x5];
1385 u8 ext_stride_num_range[0x1];
1386 u8 reserved_at_3a1[0x2];
1387 u8 log_max_stride_sz_rq[0x5];
1388 u8 reserved_at_3a8[0x3];
1389 u8 log_min_stride_sz_rq[0x5];
1390 u8 reserved_at_3b0[0x3];
1391 u8 log_max_stride_sz_sq[0x5];
1392 u8 reserved_at_3b8[0x3];
1393 u8 log_min_stride_sz_sq[0x5];
1395 u8 hairpin[0x1];
1396 u8 reserved_at_3c1[0x2];
1397 u8 log_max_hairpin_queues[0x5];
1398 u8 reserved_at_3c8[0x3];
1399 u8 log_max_hairpin_wq_data_sz[0x5];
1400 u8 reserved_at_3d0[0x3];
1401 u8 log_max_hairpin_num_packets[0x5];
1402 u8 reserved_at_3d8[0x3];
1403 u8 log_max_wq_sz[0x5];
1405 u8 nic_vport_change_event[0x1];
1406 u8 disable_local_lb_uc[0x1];
1407 u8 disable_local_lb_mc[0x1];
1408 u8 log_min_hairpin_wq_data_sz[0x5];
1409 u8 reserved_at_3e8[0x3];
1410 u8 log_max_vlan_list[0x5];
1411 u8 reserved_at_3f0[0x3];
1412 u8 log_max_current_mc_list[0x5];
1413 u8 reserved_at_3f8[0x3];
1414 u8 log_max_current_uc_list[0x5];
1416 u8 general_obj_types[0x40];
1418 u8 reserved_at_440[0x20];
1420 u8 tls[0x1];
1421 u8 reserved_at_461[0x2];
1422 u8 log_max_uctx[0x5];
1423 u8 reserved_at_468[0x3];
1424 u8 log_max_umem[0x5];
1425 u8 max_num_eqs[0x10];
1427 u8 reserved_at_480[0x3];
1428 u8 log_max_l2_table[0x5];
1429 u8 reserved_at_488[0x8];
1430 u8 log_uar_page_sz[0x10];
1432 u8 reserved_at_4a0[0x20];
1433 u8 device_frequency_mhz[0x20];
1434 u8 device_frequency_khz[0x20];
1436 u8 reserved_at_500[0x20];
1437 u8 num_of_uars_per_page[0x20];
1439 u8 flex_parser_protocols[0x20];
1441 u8 max_geneve_tlv_options[0x8];
1442 u8 reserved_at_568[0x3];
1443 u8 max_geneve_tlv_option_data_len[0x5];
1444 u8 reserved_at_570[0x10];
1446 u8 reserved_at_580[0x33];
1447 u8 log_max_dek[0x5];
1448 u8 reserved_at_5b8[0x4];
1449 u8 mini_cqe_resp_stride_index[0x1];
1450 u8 cqe_128_always[0x1];
1451 u8 cqe_compression_128[0x1];
1452 u8 cqe_compression[0x1];
1454 u8 cqe_compression_timeout[0x10];
1455 u8 cqe_compression_max_num[0x10];
1457 u8 reserved_at_5e0[0x10];
1458 u8 tag_matching[0x1];
1459 u8 rndv_offload_rc[0x1];
1460 u8 rndv_offload_dc[0x1];
1461 u8 log_tag_matching_list_sz[0x5];
1462 u8 reserved_at_5f8[0x3];
1463 u8 log_max_xrq[0x5];
1465 u8 affiliate_nic_vport_criteria[0x8];
1466 u8 native_port_num[0x8];
1467 u8 num_vhca_ports[0x8];
1468 u8 reserved_at_618[0x6];
1469 u8 sw_owner_id[0x1];
1470 u8 reserved_at_61f[0x1];
1472 u8 max_num_of_monitor_counters[0x10];
1473 u8 num_ppcnt_monitor_counters[0x10];
1475 u8 reserved_at_640[0x10];
1476 u8 num_q_monitor_counters[0x10];
1478 u8 reserved_at_660[0x20];
1480 u8 sf[0x1];
1481 u8 sf_set_partition[0x1];
1482 u8 reserved_at_682[0x1];
1483 u8 log_max_sf[0x5];
1484 u8 reserved_at_688[0x8];
1485 u8 log_min_sf_size[0x8];
1486 u8 max_num_sf_partitions[0x8];
1488 u8 uctx_cap[0x20];
1490 u8 reserved_at_6c0[0x4];
1491 u8 flex_parser_id_geneve_tlv_option_0[0x4];
1492 u8 flex_parser_id_icmp_dw1[0x4];
1493 u8 flex_parser_id_icmp_dw0[0x4];
1494 u8 flex_parser_id_icmpv6_dw1[0x4];
1495 u8 flex_parser_id_icmpv6_dw0[0x4];
1496 u8 flex_parser_id_outer_first_mpls_over_gre[0x4];
1497 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1499 u8 reserved_at_6e0[0x10];
1500 u8 sf_base_id[0x10];
1502 u8 reserved_at_700[0x80];
1503 u8 vhca_tunnel_commands[0x40];
1504 u8 reserved_at_7c0[0x40];
1508 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1509 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1510 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1512 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
1513 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1514 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1524 u8 destination_type[0x8];
1525 u8 destination_id[0x18];
1527 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1528 u8 packet_reformat[0x1];
1529 u8 reserved_at_22[0xe];
1530 u8 destination_eswitch_owner_vhca_id[0x10];
1534 u8 flow_counter_id[0x20];
1536 u8 reserved_at_20[0x20];
1542 u8 packet_reformat_id[0x20];
1544 u8 reserved_at_60[0x20];
1563 u8 reserved_at_a00[0x600];
1567 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1568 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1569 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1570 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1571 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1575 u8 l3_prot_type[0x1];
1576 u8 l4_prot_type[0x1];
1577 u8 selected_fields[0x1e];
1581 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1582 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1586 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1587 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1591 u8 wq_type[0x4];
1592 u8 wq_signature[0x1];
1593 u8 end_padding_mode[0x2];
1594 u8 cd_slave[0x1];
1595 u8 reserved_at_8[0x18];
1597 u8 hds_skip_first_sge[0x1];
1598 u8 log2_hds_buf_size[0x3];
1599 u8 reserved_at_24[0x7];
1600 u8 page_offset[0x5];
1601 u8 lwm[0x10];
1603 u8 reserved_at_40[0x8];
1604 u8 pd[0x18];
1606 u8 reserved_at_60[0x8];
1607 u8 uar_page[0x18];
1609 u8 dbr_addr[0x40];
1611 u8 hw_counter[0x20];
1613 u8 sw_counter[0x20];
1615 u8 reserved_at_100[0xc];
1616 u8 log_wq_stride[0x4];
1617 u8 reserved_at_110[0x3];
1618 u8 log_wq_pg_sz[0x5];
1619 u8 reserved_at_118[0x3];
1620 u8 log_wq_sz[0x5];
1622 u8 dbr_umem_valid[0x1];
1623 u8 wq_umem_valid[0x1];
1624 u8 reserved_at_122[0x1];
1625 u8 log_hairpin_num_packets[0x5];
1626 u8 reserved_at_128[0x3];
1627 u8 log_hairpin_data_sz[0x5];
1629 u8 reserved_at_130[0x4];
1630 u8 log_wqe_num_of_strides[0x4];
1631 u8 two_byte_shift_en[0x1];
1632 u8 reserved_at_139[0x4];
1633 u8 log_wqe_stride_size[0x3];
1635 u8 reserved_at_140[0x4c0];
1637 struct mlx5_ifc_cmd_pas_bits pas[0];
1641 u8 reserved_at_0[0x8];
1642 u8 rq_num[0x18];
1646 u8 reserved_at_0[0x10];
1647 u8 mac_addr_47_32[0x10];
1649 u8 mac_addr_31_0[0x20];
1653 u8 reserved_at_0[0x14];
1654 u8 vlan[0x0c];
1656 u8 reserved_at_20[0x20];
1660 u8 reserved_at_0[0xa0];
1662 u8 min_time_between_cnps[0x20];
1664 u8 reserved_at_c0[0x12];
1665 u8 cnp_dscp[0x6];
1666 u8 reserved_at_d8[0x4];
1667 u8 cnp_prio_mode[0x1];
1668 u8 cnp_802p_prio[0x3];
1670 u8 reserved_at_e0[0x720];
1674 u8 reserved_at_0[0x60];
1676 u8 reserved_at_60[0x4];
1677 u8 clamp_tgt_rate[0x1];
1678 u8 reserved_at_65[0x3];
1679 u8 clamp_tgt_rate_after_time_inc[0x1];
1680 u8 reserved_at_69[0x17];
1682 u8 reserved_at_80[0x20];
1684 u8 rpg_time_reset[0x20];
1686 u8 rpg_byte_reset[0x20];
1688 u8 rpg_threshold[0x20];
1690 u8 rpg_max_rate[0x20];
1692 u8 rpg_ai_rate[0x20];
1694 u8 rpg_hai_rate[0x20];
1696 u8 rpg_gd[0x20];
1698 u8 rpg_min_dec_fac[0x20];
1700 u8 rpg_min_rate[0x20];
1702 u8 reserved_at_1c0[0xe0];
1704 u8 rate_to_set_on_first_cnp[0x20];
1706 u8 dce_tcp_g[0x20];
1708 u8 dce_tcp_rtt[0x20];
1710 u8 rate_reduce_monitor_period[0x20];
1712 u8 reserved_at_320[0x20];
1714 u8 initial_alpha_value[0x20];
1716 u8 reserved_at_360[0x4a0];
1720 u8 reserved_at_0[0x80];
1722 u8 rppp_max_rps[0x20];
1724 u8 rpg_time_reset[0x20];
1726 u8 rpg_byte_reset[0x20];
1728 u8 rpg_threshold[0x20];
1730 u8 rpg_max_rate[0x20];
1732 u8 rpg_ai_rate[0x20];
1734 u8 rpg_hai_rate[0x20];
1736 u8 rpg_gd[0x20];
1738 u8 rpg_min_dec_fac[0x20];
1740 u8 rpg_min_rate[0x20];
1742 u8 reserved_at_1c0[0x640];
1746 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1747 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1748 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1752 u8 resize_field_select[0x20];
1756 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1757 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1758 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1759 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1763 u8 modify_field_select[0x20];
1767 u8 field_select_r_roce_np[0x20];
1771 u8 field_select_r_roce_rp[0x20];
1775 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1776 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1777 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1778 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1779 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1780 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1781 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1782 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1783 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1784 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1788 u8 field_select_8021qaurp[0x20];
1792 u8 time_since_last_clear_high[0x20];
1794 u8 time_since_last_clear_low[0x20];
1796 u8 symbol_errors_high[0x20];
1798 u8 symbol_errors_low[0x20];
1800 u8 sync_headers_errors_high[0x20];
1802 u8 sync_headers_errors_low[0x20];
1804 u8 edpl_bip_errors_lane0_high[0x20];
1806 u8 edpl_bip_errors_lane0_low[0x20];
1808 u8 edpl_bip_errors_lane1_high[0x20];
1810 u8 edpl_bip_errors_lane1_low[0x20];
1812 u8 edpl_bip_errors_lane2_high[0x20];
1814 u8 edpl_bip_errors_lane2_low[0x20];
1816 u8 edpl_bip_errors_lane3_high[0x20];
1818 u8 edpl_bip_errors_lane3_low[0x20];
1820 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1822 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1824 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1826 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1828 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1830 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1832 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1834 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1836 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1838 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1840 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1842 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1844 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1846 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1848 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1850 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1852 u8 rs_fec_corrected_blocks_high[0x20];
1854 u8 rs_fec_corrected_blocks_low[0x20];
1856 u8 rs_fec_uncorrectable_blocks_high[0x20];
1858 u8 rs_fec_uncorrectable_blocks_low[0x20];
1860 u8 rs_fec_no_errors_blocks_high[0x20];
1862 u8 rs_fec_no_errors_blocks_low[0x20];
1864 u8 rs_fec_single_error_blocks_high[0x20];
1866 u8 rs_fec_single_error_blocks_low[0x20];
1868 u8 rs_fec_corrected_symbols_total_high[0x20];
1870 u8 rs_fec_corrected_symbols_total_low[0x20];
1872 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1874 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1876 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1878 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1880 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1882 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1884 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1886 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1888 u8 link_down_events[0x20];
1890 u8 successful_recovery_events[0x20];
1892 u8 reserved_at_640[0x180];
1896 u8 time_since_last_clear_high[0x20];
1898 u8 time_since_last_clear_low[0x20];
1900 u8 phy_received_bits_high[0x20];
1902 u8 phy_received_bits_low[0x20];
1904 u8 phy_symbol_errors_high[0x20];
1906 u8 phy_symbol_errors_low[0x20];
1908 u8 phy_corrected_bits_high[0x20];
1910 u8 phy_corrected_bits_low[0x20];
1912 u8 phy_corrected_bits_lane0_high[0x20];
1914 u8 phy_corrected_bits_lane0_low[0x20];
1916 u8 phy_corrected_bits_lane1_high[0x20];
1918 u8 phy_corrected_bits_lane1_low[0x20];
1920 u8 phy_corrected_bits_lane2_high[0x20];
1922 u8 phy_corrected_bits_lane2_low[0x20];
1924 u8 phy_corrected_bits_lane3_high[0x20];
1926 u8 phy_corrected_bits_lane3_low[0x20];
1928 u8 reserved_at_200[0x5c0];
1932 u8 symbol_error_counter[0x10];
1934 u8 link_error_recovery_counter[0x8];
1936 u8 link_downed_counter[0x8];
1938 u8 port_rcv_errors[0x10];
1940 u8 port_rcv_remote_physical_errors[0x10];
1942 u8 port_rcv_switch_relay_errors[0x10];
1944 u8 port_xmit_discards[0x10];
1946 u8 port_xmit_constraint_errors[0x8];
1948 u8 port_rcv_constraint_errors[0x8];
1950 u8 reserved_at_70[0x8];
1952 u8 link_overrun_errors[0x8];
1954 u8 reserved_at_80[0x10];
1956 u8 vl_15_dropped[0x10];
1958 u8 reserved_at_a0[0x80];
1960 u8 port_xmit_wait[0x20];
1964 u8 transmit_queue_high[0x20];
1966 u8 transmit_queue_low[0x20];
1968 u8 no_buffer_discard_uc_high[0x20];
1970 u8 no_buffer_discard_uc_low[0x20];
1972 u8 reserved_at_80[0x740];
1976 u8 wred_discard_high[0x20];
1978 u8 wred_discard_low[0x20];
1980 u8 ecn_marked_tc_high[0x20];
1982 u8 ecn_marked_tc_low[0x20];
1984 u8 reserved_at_80[0x740];
1988 u8 rx_octets_high[0x20];
1990 u8 rx_octets_low[0x20];
1992 u8 reserved_at_40[0xc0];
1994 u8 rx_frames_high[0x20];
1996 u8 rx_frames_low[0x20];
1998 u8 tx_octets_high[0x20];
2000 u8 tx_octets_low[0x20];
2002 u8 reserved_at_180[0xc0];
2004 u8 tx_frames_high[0x20];
2006 u8 tx_frames_low[0x20];
2008 u8 rx_pause_high[0x20];
2010 u8 rx_pause_low[0x20];
2012 u8 rx_pause_duration_high[0x20];
2014 u8 rx_pause_duration_low[0x20];
2016 u8 tx_pause_high[0x20];
2018 u8 tx_pause_low[0x20];
2020 u8 tx_pause_duration_high[0x20];
2022 u8 tx_pause_duration_low[0x20];
2024 u8 rx_pause_transition_high[0x20];
2026 u8 rx_pause_transition_low[0x20];
2028 u8 reserved_at_3c0[0x40];
2030 u8 device_stall_minor_watermark_cnt_high[0x20];
2032 u8 device_stall_minor_watermark_cnt_low[0x20];
2034 u8 device_stall_critical_watermark_cnt_high[0x20];
2036 u8 device_stall_critical_watermark_cnt_low[0x20];
2038 u8 reserved_at_480[0x340];
2042 u8 port_transmit_wait_high[0x20];
2044 u8 port_transmit_wait_low[0x20];
2046 u8 reserved_at_40[0x100];
2048 u8 rx_buffer_almost_full_high[0x20];
2050 u8 rx_buffer_almost_full_low[0x20];
2052 u8 rx_buffer_full_high[0x20];
2054 u8 rx_buffer_full_low[0x20];
2056 u8 rx_icrc_encapsulated_high[0x20];
2058 u8 rx_icrc_encapsulated_low[0x20];
2060 u8 reserved_at_200[0x5c0];
2064 u8 dot3stats_alignment_errors_high[0x20];
2066 u8 dot3stats_alignment_errors_low[0x20];
2068 u8 dot3stats_fcs_errors_high[0x20];
2070 u8 dot3stats_fcs_errors_low[0x20];
2072 u8 dot3stats_single_collision_frames_high[0x20];
2074 u8 dot3stats_single_collision_frames_low[0x20];
2076 u8 dot3stats_multiple_collision_frames_high[0x20];
2078 u8 dot3stats_multiple_collision_frames_low[0x20];
2080 u8 dot3stats_sqe_test_errors_high[0x20];
2082 u8 dot3stats_sqe_test_errors_low[0x20];
2084 u8 dot3stats_deferred_transmissions_high[0x20];
2086 u8 dot3stats_deferred_transmissions_low[0x20];
2088 u8 dot3stats_late_collisions_high[0x20];
2090 u8 dot3stats_late_collisions_low[0x20];
2092 u8 dot3stats_excessive_collisions_high[0x20];
2094 u8 dot3stats_excessive_collisions_low[0x20];
2096 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
2098 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
2100 u8 dot3stats_carrier_sense_errors_high[0x20];
2102 u8 dot3stats_carrier_sense_errors_low[0x20];
2104 u8 dot3stats_frame_too_longs_high[0x20];
2106 u8 dot3stats_frame_too_longs_low[0x20];
2108 u8 dot3stats_internal_mac_receive_errors_high[0x20];
2110 u8 dot3stats_internal_mac_receive_errors_low[0x20];
2112 u8 dot3stats_symbol_errors_high[0x20];
2114 u8 dot3stats_symbol_errors_low[0x20];
2116 u8 dot3control_in_unknown_opcodes_high[0x20];
2118 u8 dot3control_in_unknown_opcodes_low[0x20];
2120 u8 dot3in_pause_frames_high[0x20];
2122 u8 dot3in_pause_frames_low[0x20];
2124 u8 dot3out_pause_frames_high[0x20];
2126 u8 dot3out_pause_frames_low[0x20];
2128 u8 reserved_at_400[0x3c0];
2132 u8 ether_stats_drop_events_high[0x20];
2134 u8 ether_stats_drop_events_low[0x20];
2136 u8 ether_stats_octets_high[0x20];
2138 u8 ether_stats_octets_low[0x20];
2140 u8 ether_stats_pkts_high[0x20];
2142 u8 ether_stats_pkts_low[0x20];
2144 u8 ether_stats_broadcast_pkts_high[0x20];
2146 u8 ether_stats_broadcast_pkts_low[0x20];
2148 u8 ether_stats_multicast_pkts_high[0x20];
2150 u8 ether_stats_multicast_pkts_low[0x20];
2152 u8 ether_stats_crc_align_errors_high[0x20];
2154 u8 ether_stats_crc_align_errors_low[0x20];
2156 u8 ether_stats_undersize_pkts_high[0x20];
2158 u8 ether_stats_undersize_pkts_low[0x20];
2160 u8 ether_stats_oversize_pkts_high[0x20];
2162 u8 ether_stats_oversize_pkts_low[0x20];
2164 u8 ether_stats_fragments_high[0x20];
2166 u8 ether_stats_fragments_low[0x20];
2168 u8 ether_stats_jabbers_high[0x20];
2170 u8 ether_stats_jabbers_low[0x20];
2172 u8 ether_stats_collisions_high[0x20];
2174 u8 ether_stats_collisions_low[0x20];
2176 u8 ether_stats_pkts64octets_high[0x20];
2178 u8 ether_stats_pkts64octets_low[0x20];
2180 u8 ether_stats_pkts65to127octets_high[0x20];
2182 u8 ether_stats_pkts65to127octets_low[0x20];
2184 u8 ether_stats_pkts128to255octets_high[0x20];
2186 u8 ether_stats_pkts128to255octets_low[0x20];
2188 u8 ether_stats_pkts256to511octets_high[0x20];
2190 u8 ether_stats_pkts256to511octets_low[0x20];
2192 u8 ether_stats_pkts512to1023octets_high[0x20];
2194 u8 ether_stats_pkts512to1023octets_low[0x20];
2196 u8 ether_stats_pkts1024to1518octets_high[0x20];
2198 u8 ether_stats_pkts1024to1518octets_low[0x20];
2200 u8 ether_stats_pkts1519to2047octets_high[0x20];
2202 u8 ether_stats_pkts1519to2047octets_low[0x20];
2204 u8 ether_stats_pkts2048to4095octets_high[0x20];
2206 u8 ether_stats_pkts2048to4095octets_low[0x20];
2208 u8 ether_stats_pkts4096to8191octets_high[0x20];
2210 u8 ether_stats_pkts4096to8191octets_low[0x20];
2212 u8 ether_stats_pkts8192to10239octets_high[0x20];
2214 u8 ether_stats_pkts8192to10239octets_low[0x20];
2216 u8 reserved_at_540[0x280];
2220 u8 if_in_octets_high[0x20];
2222 u8 if_in_octets_low[0x20];
2224 u8 if_in_ucast_pkts_high[0x20];
2226 u8 if_in_ucast_pkts_low[0x20];
2228 u8 if_in_discards_high[0x20];
2230 u8 if_in_discards_low[0x20];
2232 u8 if_in_errors_high[0x20];
2234 u8 if_in_errors_low[0x20];
2236 u8 if_in_unknown_protos_high[0x20];
2238 u8 if_in_unknown_protos_low[0x20];
2240 u8 if_out_octets_high[0x20];
2242 u8 if_out_octets_low[0x20];
2244 u8 if_out_ucast_pkts_high[0x20];
2246 u8 if_out_ucast_pkts_low[0x20];
2248 u8 if_out_discards_high[0x20];
2250 u8 if_out_discards_low[0x20];
2252 u8 if_out_errors_high[0x20];
2254 u8 if_out_errors_low[0x20];
2256 u8 if_in_multicast_pkts_high[0x20];
2258 u8 if_in_multicast_pkts_low[0x20];
2260 u8 if_in_broadcast_pkts_high[0x20];
2262 u8 if_in_broadcast_pkts_low[0x20];
2264 u8 if_out_multicast_pkts_high[0x20];
2266 u8 if_out_multicast_pkts_low[0x20];
2268 u8 if_out_broadcast_pkts_high[0x20];
2270 u8 if_out_broadcast_pkts_low[0x20];
2272 u8 reserved_at_340[0x480];
2276 u8 a_frames_transmitted_ok_high[0x20];
2278 u8 a_frames_transmitted_ok_low[0x20];
2280 u8 a_frames_received_ok_high[0x20];
2282 u8 a_frames_received_ok_low[0x20];
2284 u8 a_frame_check_sequence_errors_high[0x20];
2286 u8 a_frame_check_sequence_errors_low[0x20];
2288 u8 a_alignment_errors_high[0x20];
2290 u8 a_alignment_errors_low[0x20];
2292 u8 a_octets_transmitted_ok_high[0x20];
2294 u8 a_octets_transmitted_ok_low[0x20];
2296 u8 a_octets_received_ok_high[0x20];
2298 u8 a_octets_received_ok_low[0x20];
2300 u8 a_multicast_frames_xmitted_ok_high[0x20];
2302 u8 a_multicast_frames_xmitted_ok_low[0x20];
2304 u8 a_broadcast_frames_xmitted_ok_high[0x20];
2306 u8 a_broadcast_frames_xmitted_ok_low[0x20];
2308 u8 a_multicast_frames_received_ok_high[0x20];
2310 u8 a_multicast_frames_received_ok_low[0x20];
2312 u8 a_broadcast_frames_received_ok_high[0x20];
2314 u8 a_broadcast_frames_received_ok_low[0x20];
2316 u8 a_in_range_length_errors_high[0x20];
2318 u8 a_in_range_length_errors_low[0x20];
2320 u8 a_out_of_range_length_field_high[0x20];
2322 u8 a_out_of_range_length_field_low[0x20];
2324 u8 a_frame_too_long_errors_high[0x20];
2326 u8 a_frame_too_long_errors_low[0x20];
2328 u8 a_symbol_error_during_carrier_high[0x20];
2330 u8 a_symbol_error_during_carrier_low[0x20];
2332 u8 a_mac_control_frames_transmitted_high[0x20];
2334 u8 a_mac_control_frames_transmitted_low[0x20];
2336 u8 a_mac_control_frames_received_high[0x20];
2338 u8 a_mac_control_frames_received_low[0x20];
2340 u8 a_unsupported_opcodes_received_high[0x20];
2342 u8 a_unsupported_opcodes_received_low[0x20];
2344 u8 a_pause_mac_ctrl_frames_received_high[0x20];
2346 u8 a_pause_mac_ctrl_frames_received_low[0x20];
2348 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
2350 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
2352 u8 reserved_at_4c0[0x300];
2356 u8 life_time_counter_high[0x20];
2358 u8 life_time_counter_low[0x20];
2360 u8 rx_errors[0x20];
2362 u8 tx_errors[0x20];
2364 u8 l0_to_recovery_eieos[0x20];
2366 u8 l0_to_recovery_ts[0x20];
2368 u8 l0_to_recovery_framing[0x20];
2370 u8 l0_to_recovery_retrain[0x20];
2372 u8 crc_error_dllp[0x20];
2374 u8 crc_error_tlp[0x20];
2376 u8 tx_overflow_buffer_pkt_high[0x20];
2378 u8 tx_overflow_buffer_pkt_low[0x20];
2380 u8 outbound_stalled_reads[0x20];
2382 u8 outbound_stalled_writes[0x20];
2384 u8 outbound_stalled_reads_events[0x20];
2386 u8 outbound_stalled_writes_events[0x20];
2388 u8 reserved_at_200[0x5c0];
2392 u8 command_completion_vector[0x20];
2394 u8 reserved_at_20[0xc0];
2398 u8 reserved_at_0[0x18];
2399 u8 port_num[0x1];
2400 u8 reserved_at_19[0x3];
2401 u8 vl[0x4];
2403 u8 reserved_at_20[0xa0];
2407 u8 event_subtype[0x8];
2408 u8 reserved_at_8[0x8];
2409 u8 congestion_level[0x8];
2410 u8 reserved_at_18[0x8];
2412 u8 reserved_at_20[0xa0];
2416 u8 reserved_at_0[0x60];
2418 u8 gpio_event_hi[0x20];
2420 u8 gpio_event_lo[0x20];
2422 u8 reserved_at_a0[0x40];
2426 u8 reserved_at_0[0x40];
2428 u8 port_num[0x4];
2429 u8 reserved_at_44[0x1c];
2431 u8 reserved_at_60[0x80];
2435 u8 reserved_at_0[0xe0];
2439 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2440 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2444 u8 reserved_at_0[0x8];
2445 u8 cqn[0x18];
2447 u8 reserved_at_20[0x20];
2449 u8 reserved_at_40[0x18];
2450 u8 syndrome[0x8];
2452 u8 reserved_at_60[0x80];
2456 u8 bytes_committed[0x20];
2458 u8 r_key[0x20];
2460 u8 reserved_at_40[0x10];
2461 u8 packet_len[0x10];
2463 u8 rdma_op_len[0x20];
2465 u8 rdma_va[0x40];
2467 u8 reserved_at_c0[0x5];
2468 u8 rdma[0x1];
2469 u8 write[0x1];
2470 u8 requestor[0x1];
2471 u8 qp_number[0x18];
2475 u8 bytes_committed[0x20];
2477 u8 reserved_at_20[0x10];
2478 u8 wqe_index[0x10];
2480 u8 reserved_at_40[0x10];
2481 u8 len[0x10];
2483 u8 reserved_at_60[0x60];
2485 u8 reserved_at_c0[0x5];
2486 u8 rdma[0x1];
2487 u8 write_read[0x1];
2488 u8 requestor[0x1];
2489 u8 qpn[0x18];
2493 u8 reserved_at_0[0xa0];
2495 u8 type[0x8];
2496 u8 reserved_at_a8[0x18];
2498 u8 reserved_at_c0[0x8];
2499 u8 qpn_rqn_sqn[0x18];
2503 u8 reserved_at_0[0xc0];
2505 u8 reserved_at_c0[0x8];
2506 u8 dct_number[0x18];
2510 u8 reserved_at_0[0xc0];
2512 u8 reserved_at_c0[0x8];
2513 u8 cq_number[0x18];
2517 MLX5_QPC_STATE_RST = 0x0,
2518 MLX5_QPC_STATE_INIT = 0x1,
2519 MLX5_QPC_STATE_RTR = 0x2,
2520 MLX5_QPC_STATE_RTS = 0x3,
2521 MLX5_QPC_STATE_SQER = 0x4,
2522 MLX5_QPC_STATE_ERR = 0x6,
2523 MLX5_QPC_STATE_SQD = 0x7,
2524 MLX5_QPC_STATE_SUSPENDED = 0x9,
2528 MLX5_QPC_ST_RC = 0x0,
2529 MLX5_QPC_ST_UC = 0x1,
2530 MLX5_QPC_ST_UD = 0x2,
2531 MLX5_QPC_ST_XRC = 0x3,
2532 MLX5_QPC_ST_DCI = 0x5,
2533 MLX5_QPC_ST_QP0 = 0x7,
2534 MLX5_QPC_ST_QP1 = 0x8,
2535 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2536 MLX5_QPC_ST_REG_UMR = 0xc,
2540 MLX5_QPC_PM_STATE_ARMED = 0x0,
2541 MLX5_QPC_PM_STATE_REARM = 0x1,
2542 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2543 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2547 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2551 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2552 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2556 MLX5_QPC_MTU_256_BYTES = 0x1,
2557 MLX5_QPC_MTU_512_BYTES = 0x2,
2558 MLX5_QPC_MTU_1K_BYTES = 0x3,
2559 MLX5_QPC_MTU_2K_BYTES = 0x4,
2560 MLX5_QPC_MTU_4K_BYTES = 0x5,
2561 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2565 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2566 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2567 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2568 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2569 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2570 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2571 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2572 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2576 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2577 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2578 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2582 MLX5_QPC_CS_RES_DISABLE = 0x0,
2583 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2584 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2588 u8 state[0x4];
2589 u8 lag_tx_port_affinity[0x4];
2590 u8 st[0x8];
2591 u8 reserved_at_10[0x3];
2592 u8 pm_state[0x2];
2593 u8 reserved_at_15[0x1];
2594 u8 req_e2e_credit_mode[0x2];
2595 u8 offload_type[0x4];
2596 u8 end_padding_mode[0x2];
2597 u8 reserved_at_1e[0x2];
2599 u8 wq_signature[0x1];
2600 u8 block_lb_mc[0x1];
2601 u8 atomic_like_write_en[0x1];
2602 u8 latency_sensitive[0x1];
2603 u8 reserved_at_24[0x1];
2604 u8 drain_sigerr[0x1];
2605 u8 reserved_at_26[0x2];
2606 u8 pd[0x18];
2608 u8 mtu[0x3];
2609 u8 log_msg_max[0x5];
2610 u8 reserved_at_48[0x1];
2611 u8 log_rq_size[0x4];
2612 u8 log_rq_stride[0x3];
2613 u8 no_sq[0x1];
2614 u8 log_sq_size[0x4];
2615 u8 reserved_at_55[0x6];
2616 u8 rlky[0x1];
2617 u8 ulp_stateless_offload_mode[0x4];
2619 u8 counter_set_id[0x8];
2620 u8 uar_page[0x18];
2622 u8 reserved_at_80[0x8];
2623 u8 user_index[0x18];
2625 u8 reserved_at_a0[0x3];
2626 u8 log_page_size[0x5];
2627 u8 remote_qpn[0x18];
2633 u8 log_ack_req_freq[0x4];
2634 u8 reserved_at_384[0x4];
2635 u8 log_sra_max[0x3];
2636 u8 reserved_at_38b[0x2];
2637 u8 retry_count[0x3];
2638 u8 rnr_retry[0x3];
2639 u8 reserved_at_393[0x1];
2640 u8 fre[0x1];
2641 u8 cur_rnr_retry[0x3];
2642 u8 cur_retry_count[0x3];
2643 u8 reserved_at_39b[0x5];
2645 u8 reserved_at_3a0[0x20];
2647 u8 reserved_at_3c0[0x8];
2648 u8 next_send_psn[0x18];
2650 u8 reserved_at_3e0[0x8];
2651 u8 cqn_snd[0x18];
2653 u8 reserved_at_400[0x8];
2654 u8 deth_sqpn[0x18];
2656 u8 reserved_at_420[0x20];
2658 u8 reserved_at_440[0x8];
2659 u8 last_acked_psn[0x18];
2661 u8 reserved_at_460[0x8];
2662 u8 ssn[0x18];
2664 u8 reserved_at_480[0x8];
2665 u8 log_rra_max[0x3];
2666 u8 reserved_at_48b[0x1];
2667 u8 atomic_mode[0x4];
2668 u8 rre[0x1];
2669 u8 rwe[0x1];
2670 u8 rae[0x1];
2671 u8 reserved_at_493[0x1];
2672 u8 page_offset[0x6];
2673 u8 reserved_at_49a[0x3];
2674 u8 cd_slave_receive[0x1];
2675 u8 cd_slave_send[0x1];
2676 u8 cd_master[0x1];
2678 u8 reserved_at_4a0[0x3];
2679 u8 min_rnr_nak[0x5];
2680 u8 next_rcv_psn[0x18];
2682 u8 reserved_at_4c0[0x8];
2683 u8 xrcd[0x18];
2685 u8 reserved_at_4e0[0x8];
2686 u8 cqn_rcv[0x18];
2688 u8 dbr_addr[0x40];
2690 u8 q_key[0x20];
2692 u8 reserved_at_560[0x5];
2693 u8 rq_type[0x3];
2694 u8 srqn_rmpn_xrqn[0x18];
2696 u8 reserved_at_580[0x8];
2697 u8 rmsn[0x18];
2699 u8 hw_sq_wqebb_counter[0x10];
2700 u8 sw_sq_wqebb_counter[0x10];
2702 u8 hw_rq_counter[0x20];
2704 u8 sw_rq_counter[0x20];
2706 u8 reserved_at_600[0x20];
2708 u8 reserved_at_620[0xf];
2709 u8 cgs[0x1];
2710 u8 cs_req[0x8];
2711 u8 cs_res[0x8];
2713 u8 dc_access_key[0x40];
2715 u8 reserved_at_680[0x3];
2716 u8 dbr_umem_valid[0x1];
2718 u8 reserved_at_684[0xbc];
2722 u8 source_l3_address[16][0x8];
2724 u8 reserved_at_80[0x3];
2725 u8 vlan_valid[0x1];
2726 u8 vlan_id[0xc];
2727 u8 source_mac_47_32[0x10];
2729 u8 source_mac_31_0[0x20];
2731 u8 reserved_at_c0[0x14];
2732 u8 roce_l3_type[0x4];
2733 u8 roce_version[0x8];
2735 u8 reserved_at_e0[0x20];
2753 u8 reserved_at_0[0x8000];
2757 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2758 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2759 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2760 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2761 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2762 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2763 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
2764 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
2765 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2766 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
2767 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2771 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0,
2772 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1,
2773 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2,
2777 u8 ethtype[0x10];
2778 u8 prio[0x3];
2779 u8 cfi[0x1];
2780 u8 vid[0xc];
2786 u8 group_id[0x20];
2788 u8 reserved_at_40[0x8];
2789 u8 flow_tag[0x18];
2791 u8 reserved_at_60[0x10];
2792 u8 action[0x10];
2794 u8 extended_destination[0x1];
2795 u8 reserved_at_81[0x1];
2796 u8 flow_source[0x2];
2797 u8 reserved_at_84[0x4];
2798 u8 destination_list_size[0x18];
2800 u8 reserved_at_a0[0x8];
2801 u8 flow_counter_list_size[0x18];
2803 u8 packet_reformat_id[0x20];
2805 u8 modify_header_id[0x20];
2809 u8 reserved_at_120[0xe0];
2813 u8 reserved_at_1200[0x600];
2815 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2819 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2820 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2824 u8 state[0x4];
2825 u8 log_xrc_srq_size[0x4];
2826 u8 reserved_at_8[0x18];
2828 u8 wq_signature[0x1];
2829 u8 cont_srq[0x1];
2830 u8 reserved_at_22[0x1];
2831 u8 rlky[0x1];
2832 u8 basic_cyclic_rcv_wqe[0x1];
2833 u8 log_rq_stride[0x3];
2834 u8 xrcd[0x18];
2836 u8 page_offset[0x6];
2837 u8 reserved_at_46[0x1];
2838 u8 dbr_umem_valid[0x1];
2839 u8 cqn[0x18];
2841 u8 reserved_at_60[0x20];
2843 u8 user_index_equal_xrc_srqn[0x1];
2844 u8 reserved_at_81[0x1];
2845 u8 log_page_size[0x6];
2846 u8 user_index[0x18];
2848 u8 reserved_at_a0[0x20];
2850 u8 reserved_at_c0[0x8];
2851 u8 pd[0x18];
2853 u8 lwm[0x10];
2854 u8 wqe_cnt[0x10];
2856 u8 reserved_at_100[0x40];
2858 u8 db_record_addr_h[0x20];
2860 u8 db_record_addr_l[0x1e];
2861 u8 reserved_at_17e[0x2];
2863 u8 reserved_at_180[0x80];
2867 u8 counter_error_queues[0x20];
2869 u8 total_error_queues[0x20];
2871 u8 send_queue_priority_update_flow[0x20];
2873 u8 reserved_at_60[0x20];
2875 u8 nic_receive_steering_discard[0x40];
2877 u8 receive_discard_vport_down[0x40];
2879 u8 transmit_discard_vport_down[0x40];
2881 u8 reserved_at_140[0xa0];
2883 u8 internal_rq_out_of_buffer[0x20];
2885 u8 reserved_at_200[0xe00];
2889 u8 packets[0x40];
2891 u8 octets[0x40];
2895 u8 strict_lag_tx_port_affinity[0x1];
2896 u8 tls_en[0x1];
2897 u8 reserved_at_2[0x2];
2898 u8 lag_tx_port_affinity[0x04];
2900 u8 reserved_at_8[0x4];
2901 u8 prio[0x4];
2902 u8 reserved_at_10[0x10];
2904 u8 reserved_at_20[0x100];
2906 u8 reserved_at_120[0x8];
2907 u8 transport_domain[0x18];
2909 u8 reserved_at_140[0x8];
2910 u8 underlay_qpn[0x18];
2912 u8 reserved_at_160[0x8];
2913 u8 pd[0x18];
2915 u8 reserved_at_180[0x380];
2919 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2920 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2924 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2925 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2929 MLX5_RX_HASH_FN_NONE = 0x0,
2930 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2931 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2935 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
2936 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
2940 u8 reserved_at_0[0x20];
2942 u8 disp_type[0x4];
2943 u8 reserved_at_24[0x1c];
2945 u8 reserved_at_40[0x40];
2947 u8 reserved_at_80[0x4];
2948 u8 lro_timeout_period_usecs[0x10];
2949 u8 lro_enable_mask[0x4];
2950 u8 lro_max_ip_payload_size[0x8];
2952 u8 reserved_at_a0[0x40];
2954 u8 reserved_at_e0[0x8];
2955 u8 inline_rqn[0x18];
2957 u8 rx_hash_symmetric[0x1];
2958 u8 reserved_at_101[0x1];
2959 u8 tunneled_offload_en[0x1];
2960 u8 reserved_at_103[0x5];
2961 u8 indirect_table[0x18];
2963 u8 rx_hash_fn[0x4];
2964 u8 reserved_at_124[0x2];
2965 u8 self_lb_block[0x2];
2966 u8 transport_domain[0x18];
2968 u8 rx_hash_toeplitz_key[10][0x20];
2974 u8 reserved_at_2c0[0x4c0];
2978 MLX5_SRQC_STATE_GOOD = 0x0,
2979 MLX5_SRQC_STATE_ERROR = 0x1,
2983 u8 state[0x4];
2984 u8 log_srq_size[0x4];
2985 u8 reserved_at_8[0x18];
2987 u8 wq_signature[0x1];
2988 u8 cont_srq[0x1];
2989 u8 reserved_at_22[0x1];
2990 u8 rlky[0x1];
2991 u8 reserved_at_24[0x1];
2992 u8 log_rq_stride[0x3];
2993 u8 xrcd[0x18];
2995 u8 page_offset[0x6];
2996 u8 reserved_at_46[0x2];
2997 u8 cqn[0x18];
2999 u8 reserved_at_60[0x20];
3001 u8 reserved_at_80[0x2];
3002 u8 log_page_size[0x6];
3003 u8 reserved_at_88[0x18];
3005 u8 reserved_at_a0[0x20];
3007 u8 reserved_at_c0[0x8];
3008 u8 pd[0x18];
3010 u8 lwm[0x10];
3011 u8 wqe_cnt[0x10];
3013 u8 reserved_at_100[0x40];
3015 u8 dbr_addr[0x40];
3017 u8 reserved_at_180[0x80];
3021 MLX5_SQC_STATE_RST = 0x0,
3022 MLX5_SQC_STATE_RDY = 0x1,
3023 MLX5_SQC_STATE_ERR = 0x3,
3027 u8 rlky[0x1];
3028 u8 cd_master[0x1];
3029 u8 fre[0x1];
3030 u8 flush_in_error_en[0x1];
3031 u8 allow_multi_pkt_send_wqe[0x1];
3032 u8 min_wqe_inline_mode[0x3];
3033 u8 state[0x4];
3034 u8 reg_umr[0x1];
3035 u8 allow_swp[0x1];
3036 u8 hairpin[0x1];
3037 u8 reserved_at_f[0x11];
3039 u8 reserved_at_20[0x8];
3040 u8 user_index[0x18];
3042 u8 reserved_at_40[0x8];
3043 u8 cqn[0x18];
3045 u8 reserved_at_60[0x8];
3046 u8 hairpin_peer_rq[0x18];
3048 u8 reserved_at_80[0x10];
3049 u8 hairpin_peer_vhca[0x10];
3051 u8 reserved_at_a0[0x50];
3053 u8 packet_pacing_rate_limit_index[0x10];
3054 u8 tis_lst_sz[0x10];
3055 u8 reserved_at_110[0x10];
3057 u8 reserved_at_120[0x40];
3059 u8 reserved_at_160[0x8];
3060 u8 tis_num_0[0x18];
3066 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3067 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3068 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3069 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3073 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0,
3080 u8 element_type[0x8];
3081 u8 reserved_at_8[0x18];
3083 u8 element_attributes[0x20];
3085 u8 parent_element_id[0x20];
3087 u8 reserved_at_60[0x40];
3089 u8 bw_share[0x20];
3091 u8 max_average_bw[0x20];
3093 u8 reserved_at_e0[0x120];
3097 u8 reserved_at_0[0xa0];
3099 u8 reserved_at_a0[0x10];
3100 u8 rqt_max_size[0x10];
3102 u8 reserved_at_c0[0x10];
3103 u8 rqt_actual_size[0x10];
3105 u8 reserved_at_e0[0x6a0];
3107 struct mlx5_ifc_rq_num_bits rq_num[0];
3111 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
3112 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
3116 MLX5_RQC_STATE_RST = 0x0,
3117 MLX5_RQC_STATE_RDY = 0x1,
3118 MLX5_RQC_STATE_ERR = 0x3,
3122 u8 rlky[0x1];
3123 u8 delay_drop_en[0x1];
3124 u8 scatter_fcs[0x1];
3125 u8 vsd[0x1];
3126 u8 mem_rq_type[0x4];
3127 u8 state[0x4];
3128 u8 reserved_at_c[0x1];
3129 u8 flush_in_error_en[0x1];
3130 u8 hairpin[0x1];
3131 u8 reserved_at_f[0x11];
3133 u8 reserved_at_20[0x8];
3134 u8 user_index[0x18];
3136 u8 reserved_at_40[0x8];
3137 u8 cqn[0x18];
3139 u8 counter_set_id[0x8];
3140 u8 reserved_at_68[0x18];
3142 u8 reserved_at_80[0x8];
3143 u8 rmpn[0x18];
3145 u8 reserved_at_a0[0x8];
3146 u8 hairpin_peer_sq[0x18];
3148 u8 reserved_at_c0[0x10];
3149 u8 hairpin_peer_vhca[0x10];
3151 u8 reserved_at_e0[0xa0];
3157 MLX5_RMPC_STATE_RDY = 0x1,
3158 MLX5_RMPC_STATE_ERR = 0x3,
3162 u8 reserved_at_0[0x8];
3163 u8 state[0x4];
3164 u8 reserved_at_c[0x14];
3166 u8 basic_cyclic_rcv_wqe[0x1];
3167 u8 reserved_at_21[0x1f];
3169 u8 reserved_at_40[0x140];
3175 u8 reserved_at_0[0x5];
3176 u8 min_wqe_inline_mode[0x3];
3177 u8 reserved_at_8[0x15];
3178 u8 disable_mc_local_lb[0x1];
3179 u8 disable_uc_local_lb[0x1];
3180 u8 roce_en[0x1];
3182 u8 arm_change_event[0x1];
3183 u8 reserved_at_21[0x1a];
3184 u8 event_on_mtu[0x1];
3185 u8 event_on_promisc_change[0x1];
3186 u8 event_on_vlan_change[0x1];
3187 u8 event_on_mc_address_change[0x1];
3188 u8 event_on_uc_address_change[0x1];
3190 u8 reserved_at_40[0xc];
3192 u8 affiliation_criteria[0x4];
3193 u8 affiliated_vhca_id[0x10];
3195 u8 reserved_at_60[0xd0];
3197 u8 mtu[0x10];
3199 u8 system_image_guid[0x40];
3200 u8 port_guid[0x40];
3201 u8 node_guid[0x40];
3203 u8 reserved_at_200[0x140];
3204 u8 qkey_violation_counter[0x10];
3205 u8 reserved_at_350[0x430];
3207 u8 promisc_uc[0x1];
3208 u8 promisc_mc[0x1];
3209 u8 promisc_all[0x1];
3210 u8 reserved_at_783[0x2];
3211 u8 allowed_list_type[0x3];
3212 u8 reserved_at_788[0xc];
3213 u8 allowed_list_size[0xc];
3217 u8 reserved_at_7e0[0x20];
3219 u8 current_uc_mac_address[0][0x40];
3223 MLX5_MKC_ACCESS_MODE_PA = 0x0,
3224 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
3225 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
3226 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
3227 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3228 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3232 u8 reserved_at_0[0x1];
3233 u8 free[0x1];
3234 u8 reserved_at_2[0x1];
3235 u8 access_mode_4_2[0x3];
3236 u8 reserved_at_6[0x7];
3237 u8 relaxed_ordering_write[0x1];
3238 u8 reserved_at_e[0x1];
3239 u8 small_fence_on_rdma_read_response[0x1];
3240 u8 umr_en[0x1];
3241 u8 a[0x1];
3242 u8 rw[0x1];
3243 u8 rr[0x1];
3244 u8 lw[0x1];
3245 u8 lr[0x1];
3246 u8 access_mode_1_0[0x2];
3247 u8 reserved_at_18[0x8];
3249 u8 qpn[0x18];
3250 u8 mkey_7_0[0x8];
3252 u8 reserved_at_40[0x20];
3254 u8 length64[0x1];
3255 u8 bsf_en[0x1];
3256 u8 sync_umr[0x1];
3257 u8 reserved_at_63[0x2];
3258 u8 expected_sigerr_count[0x1];
3259 u8 reserved_at_66[0x1];
3260 u8 en_rinval[0x1];
3261 u8 pd[0x18];
3263 u8 start_addr[0x40];
3265 u8 len[0x40];
3267 u8 bsf_octword_size[0x20];
3269 u8 reserved_at_120[0x80];
3271 u8 translations_octword_size[0x20];
3273 u8 reserved_at_1c0[0x1b];
3274 u8 log_page_size[0x5];
3276 u8 reserved_at_1e0[0x20];
3280 u8 reserved_at_0[0x10];
3281 u8 pkey[0x10];
3285 u8 array128_auto[16][0x8];
3289 u8 field_select[0x20];
3291 u8 reserved_at_20[0xe0];
3293 u8 sm_virt_aware[0x1];
3294 u8 has_smi[0x1];
3295 u8 has_raw[0x1];
3296 u8 grh_required[0x1];
3297 u8 reserved_at_104[0xc];
3298 u8 port_physical_state[0x4];
3299 u8 vport_state_policy[0x4];
3300 u8 port_state[0x4];
3301 u8 vport_state[0x4];
3303 u8 reserved_at_120[0x20];
3305 u8 system_image_guid[0x40];
3307 u8 port_guid[0x40];
3309 u8 node_guid[0x40];
3311 u8 cap_mask1[0x20];
3313 u8 cap_mask1_field_select[0x20];
3315 u8 cap_mask2[0x20];
3317 u8 cap_mask2_field_select[0x20];
3319 u8 reserved_at_280[0x80];
3321 u8 lid[0x10];
3322 u8 reserved_at_310[0x4];
3323 u8 init_type_reply[0x4];
3324 u8 lmc[0x3];
3325 u8 subnet_timeout[0x5];
3327 u8 sm_lid[0x10];
3328 u8 sm_sl[0x4];
3329 u8 reserved_at_334[0xc];
3331 u8 qkey_violation_counter[0x10];
3332 u8 pkey_violation_counter[0x10];
3334 u8 reserved_at_360[0xca0];
3338 u8 fdb_to_vport_reg_c[0x1];
3339 u8 reserved_at_1[0x2];
3340 u8 vport_svlan_strip[0x1];
3341 u8 vport_cvlan_strip[0x1];
3342 u8 vport_svlan_insert[0x1];
3343 u8 vport_cvlan_insert[0x2];
3344 u8 fdb_to_vport_reg_c_id[0x8];
3345 u8 reserved_at_10[0x10];
3347 u8 reserved_at_20[0x20];
3349 u8 svlan_cfi[0x1];
3350 u8 svlan_pcp[0x3];
3351 u8 svlan_id[0xc];
3352 u8 cvlan_cfi[0x1];
3353 u8 cvlan_pcp[0x3];
3354 u8 cvlan_id[0xc];
3356 u8 reserved_at_60[0x720];
3358 u8 sw_steering_vport_icm_address_rx[0x40];
3360 u8 sw_steering_vport_icm_address_tx[0x40];
3364 MLX5_EQC_STATUS_OK = 0x0,
3365 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
3369 MLX5_EQC_ST_ARMED = 0x9,
3370 MLX5_EQC_ST_FIRED = 0xa,
3374 u8 status[0x4];
3375 u8 reserved_at_4[0x9];
3376 u8 ec[0x1];
3377 u8 oi[0x1];
3378 u8 reserved_at_f[0x5];
3379 u8 st[0x4];
3380 u8 reserved_at_18[0x8];
3382 u8 reserved_at_20[0x20];
3384 u8 reserved_at_40[0x14];
3385 u8 page_offset[0x6];
3386 u8 reserved_at_5a[0x6];
3388 u8 reserved_at_60[0x3];
3389 u8 log_eq_size[0x5];
3390 u8 uar_page[0x18];
3392 u8 reserved_at_80[0x20];
3394 u8 reserved_at_a0[0x18];
3395 u8 intr[0x8];
3397 u8 reserved_at_c0[0x3];
3398 u8 log_page_size[0x5];
3399 u8 reserved_at_c8[0x18];
3401 u8 reserved_at_e0[0x60];
3403 u8 reserved_at_140[0x8];
3404 u8 consumer_counter[0x18];
3406 u8 reserved_at_160[0x8];
3407 u8 producer_counter[0x18];
3409 u8 reserved_at_180[0x80];
3413 MLX5_DCTC_STATE_ACTIVE = 0x0,
3414 MLX5_DCTC_STATE_DRAINING = 0x1,
3415 MLX5_DCTC_STATE_DRAINED = 0x2,
3419 MLX5_DCTC_CS_RES_DISABLE = 0x0,
3420 MLX5_DCTC_CS_RES_NA = 0x1,
3421 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
3425 MLX5_DCTC_MTU_256_BYTES = 0x1,
3426 MLX5_DCTC_MTU_512_BYTES = 0x2,
3427 MLX5_DCTC_MTU_1K_BYTES = 0x3,
3428 MLX5_DCTC_MTU_2K_BYTES = 0x4,
3429 MLX5_DCTC_MTU_4K_BYTES = 0x5,
3433 u8 reserved_at_0[0x4];
3434 u8 state[0x4];
3435 u8 reserved_at_8[0x18];
3437 u8 reserved_at_20[0x8];
3438 u8 user_index[0x18];
3440 u8 reserved_at_40[0x8];
3441 u8 cqn[0x18];
3443 u8 counter_set_id[0x8];
3444 u8 atomic_mode[0x4];
3445 u8 rre[0x1];
3446 u8 rwe[0x1];
3447 u8 rae[0x1];
3448 u8 atomic_like_write_en[0x1];
3449 u8 latency_sensitive[0x1];
3450 u8 rlky[0x1];
3451 u8 free_ar[0x1];
3452 u8 reserved_at_73[0xd];
3454 u8 reserved_at_80[0x8];
3455 u8 cs_res[0x8];
3456 u8 reserved_at_90[0x3];
3457 u8 min_rnr_nak[0x5];
3458 u8 reserved_at_98[0x8];
3460 u8 reserved_at_a0[0x8];
3461 u8 srqn_xrqn[0x18];
3463 u8 reserved_at_c0[0x8];
3464 u8 pd[0x18];
3466 u8 tclass[0x8];
3467 u8 reserved_at_e8[0x4];
3468 u8 flow_label[0x14];
3470 u8 dc_access_key[0x40];
3472 u8 reserved_at_140[0x5];
3473 u8 mtu[0x3];
3474 u8 port[0x8];
3475 u8 pkey_index[0x10];
3477 u8 reserved_at_160[0x8];
3478 u8 my_addr_index[0x8];
3479 u8 reserved_at_170[0x8];
3480 u8 hop_limit[0x8];
3482 u8 dc_access_key_violation_count[0x20];
3484 u8 reserved_at_1a0[0x14];
3485 u8 dei_cfi[0x1];
3486 u8 eth_prio[0x3];
3487 u8 ecn[0x2];
3488 u8 dscp[0x6];
3490 u8 reserved_at_1c0[0x40];
3494 MLX5_CQC_STATUS_OK = 0x0,
3495 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3496 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3500 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3501 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3505 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3506 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3507 MLX5_CQC_ST_FIRED = 0xa,
3511 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3512 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3517 u8 status[0x4];
3518 u8 reserved_at_4[0x2];
3519 u8 dbr_umem_valid[0x1];
3520 u8 reserved_at_7[0x1];
3521 u8 cqe_sz[0x3];
3522 u8 cc[0x1];
3523 u8 reserved_at_c[0x1];
3524 u8 scqe_break_moderation_en[0x1];
3525 u8 oi[0x1];
3526 u8 cq_period_mode[0x2];
3527 u8 cqe_comp_en[0x1];
3528 u8 mini_cqe_res_format[0x2];
3529 u8 st[0x4];
3530 u8 reserved_at_18[0x8];
3532 u8 reserved_at_20[0x20];
3534 u8 reserved_at_40[0x14];
3535 u8 page_offset[0x6];
3536 u8 reserved_at_5a[0x6];
3538 u8 reserved_at_60[0x3];
3539 u8 log_cq_size[0x5];
3540 u8 uar_page[0x18];
3542 u8 reserved_at_80[0x4];
3543 u8 cq_period[0xc];
3544 u8 cq_max_count[0x10];
3546 u8 reserved_at_a0[0x18];
3547 u8 c_eqn[0x8];
3549 u8 reserved_at_c0[0x3];
3550 u8 log_page_size[0x5];
3551 u8 reserved_at_c8[0x18];
3553 u8 reserved_at_e0[0x20];
3555 u8 reserved_at_100[0x8];
3556 u8 last_notified_index[0x18];
3558 u8 reserved_at_120[0x8];
3559 u8 last_solicit_index[0x18];
3561 u8 reserved_at_140[0x8];
3562 u8 consumer_counter[0x18];
3564 u8 reserved_at_160[0x8];
3565 u8 producer_counter[0x18];
3567 u8 reserved_at_180[0x40];
3569 u8 dbr_addr[0x40];
3576 u8 reserved_at_0[0x800];
3580 u8 reserved_at_0[0xc0];
3582 u8 reserved_at_c0[0x8];
3583 u8 ieee_vendor_id[0x18];
3585 u8 reserved_at_e0[0x10];
3586 u8 vsd_vendor_id[0x10];
3588 u8 vsd[208][0x8];
3590 u8 vsd_contd_psid[16][0x8];
3594 MLX5_XRQC_STATE_GOOD = 0x0,
3595 MLX5_XRQC_STATE_ERROR = 0x1,
3599 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3600 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3604 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3608 u8 log_matching_list_sz[0x4];
3609 u8 reserved_at_4[0xc];
3610 u8 append_next_index[0x10];
3612 u8 sw_phase_cnt[0x10];
3613 u8 hw_phase_cnt[0x10];
3615 u8 reserved_at_40[0x40];
3619 u8 state[0x4];
3620 u8 rlkey[0x1];
3621 u8 reserved_at_5[0xf];
3622 u8 topology[0x4];
3623 u8 reserved_at_18[0x4];
3624 u8 offload[0x4];
3626 u8 reserved_at_20[0x8];
3627 u8 user_index[0x18];
3629 u8 reserved_at_40[0x8];
3630 u8 cqn[0x18];
3632 u8 reserved_at_60[0xa0];
3636 u8 reserved_at_180[0x280];
3644 u8 reserved_at_0[0x20];
3651 u8 reserved_at_0[0x20];
3666 u8 reserved_at_0[0x7c0];
3671 u8 reserved_at_0[0x7c0];
3687 u8 reserved_at_0[0xe0];
3691 u8 reserved_at_0[0x100];
3693 u8 assert_existptr[0x20];
3695 u8 assert_callra[0x20];
3697 u8 reserved_at_140[0x40];
3699 u8 fw_version[0x20];
3701 u8 hw_id[0x20];
3703 u8 reserved_at_1c0[0x20];
3705 u8 irisc_index[0x8];
3706 u8 synd[0x8];
3707 u8 ext_synd[0x10];
3711 u8 no_lb[0x1];
3712 u8 reserved_at_1[0x7];
3713 u8 port[0x8];
3714 u8 reserved_at_10[0x10];
3716 u8 reserved_at_20[0x60];
3720 u8 traffic_class[0x4];
3721 u8 reserved_at_4[0xc];
3722 u8 vport_number[0x10];
3726 u8 reserved_at_0[0x10];
3727 u8 vport_number[0x10];
3731 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3732 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3733 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3737 u8 reserved_at_0[0x8];
3738 u8 tsar_type[0x8];
3739 u8 reserved_at_10[0x10];
3743 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3744 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3748 u8 status[0x8];
3749 u8 reserved_at_8[0x18];
3751 u8 syndrome[0x20];
3753 u8 reserved_at_40[0x3f];
3755 u8 state[0x1];
3759 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3760 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
3761 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3765 u8 opcode[0x10];
3766 u8 reserved_at_10[0x10];
3768 u8 reserved_at_20[0x10];
3769 u8 op_mod[0x10];
3771 u8 reserved_at_40[0x10];
3772 u8 profile[0x10];
3774 u8 reserved_at_60[0x20];
3778 u8 status[0x8];
3779 u8 reserved_at_8[0x18];
3781 u8 syndrome[0x20];
3783 u8 reserved_at_40[0x40];
3787 u8 opcode[0x10];
3788 u8 uid[0x10];
3790 u8 reserved_at_20[0x10];
3791 u8 op_mod[0x10];
3793 u8 reserved_at_40[0x8];
3794 u8 qpn[0x18];
3796 u8 reserved_at_60[0x20];
3798 u8 opt_param_mask[0x20];
3800 u8 reserved_at_a0[0x20];
3804 u8 reserved_at_800[0x80];
3808 u8 status[0x8];
3809 u8 reserved_at_8[0x18];
3811 u8 syndrome[0x20];
3813 u8 reserved_at_40[0x40];
3817 u8 opcode[0x10];
3818 u8 uid[0x10];
3820 u8 reserved_at_20[0x10];
3821 u8 op_mod[0x10];
3823 u8 reserved_at_40[0x8];
3824 u8 qpn[0x18];
3826 u8 reserved_at_60[0x20];
3828 u8 opt_param_mask[0x20];
3830 u8 reserved_at_a0[0x20];
3834 u8 reserved_at_800[0x80];
3838 u8 status[0x8];
3839 u8 reserved_at_8[0x18];
3841 u8 syndrome[0x20];
3843 u8 reserved_at_40[0x40];
3847 u8 opcode[0x10];
3848 u8 reserved_at_10[0x10];
3850 u8 reserved_at_20[0x10];
3851 u8 op_mod[0x10];
3853 u8 roce_address_index[0x10];
3854 u8 reserved_at_50[0xc];
3855 u8 vhca_port_num[0x4];
3857 u8 reserved_at_60[0x20];
3863 u8 status[0x8];
3864 u8 reserved_at_8[0x18];
3866 u8 syndrome[0x20];
3868 u8 reserved_at_40[0x40];
3872 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3873 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3877 u8 opcode[0x10];
3878 u8 reserved_at_10[0x10];
3880 u8 reserved_at_20[0x10];
3881 u8 op_mod[0x10];
3883 u8 reserved_at_40[0x20];
3885 u8 reserved_at_60[0x6];
3886 u8 demux_mode[0x2];
3887 u8 reserved_at_68[0x18];
3891 u8 status[0x8];
3892 u8 reserved_at_8[0x18];
3894 u8 syndrome[0x20];
3896 u8 reserved_at_40[0x40];
3900 u8 opcode[0x10];
3901 u8 reserved_at_10[0x10];
3903 u8 reserved_at_20[0x10];
3904 u8 op_mod[0x10];
3906 u8 reserved_at_40[0x60];
3908 u8 reserved_at_a0[0x8];
3909 u8 table_index[0x18];
3911 u8 reserved_at_c0[0x20];
3913 u8 reserved_at_e0[0x13];
3914 u8 vlan_valid[0x1];
3915 u8 vlan[0xc];
3919 u8 reserved_at_140[0xc0];
3923 u8 status[0x8];
3924 u8 reserved_at_8[0x18];
3926 u8 syndrome[0x20];
3928 u8 reserved_at_40[0x40];
3932 u8 opcode[0x10];
3933 u8 reserved_at_10[0x10];
3935 u8 reserved_at_20[0x10];
3936 u8 op_mod[0x10];
3938 u8 reserved_at_40[0x10];
3939 u8 current_issi[0x10];
3941 u8 reserved_at_60[0x20];
3945 u8 status[0x8];
3946 u8 reserved_at_8[0x18];
3948 u8 syndrome[0x20];
3950 u8 reserved_at_40[0x40];
3954 u8 opcode[0x10];
3955 u8 reserved_at_10[0x10];
3957 u8 reserved_at_20[0x10];
3958 u8 op_mod[0x10];
3960 u8 reserved_at_40[0x40];
3966 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3967 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3968 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3969 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3973 u8 status[0x8];
3974 u8 reserved_at_8[0x18];
3976 u8 syndrome[0x20];
3978 u8 reserved_at_40[0x40];
3982 u8 opcode[0x10];
3983 u8 reserved_at_10[0x10];
3985 u8 reserved_at_20[0x10];
3986 u8 op_mod[0x10];
3988 u8 other_vport[0x1];
3989 u8 reserved_at_41[0xf];
3990 u8 vport_number[0x10];
3992 u8 reserved_at_60[0x20];
3994 u8 table_type[0x8];
3995 u8 reserved_at_88[0x18];
3997 u8 reserved_at_a0[0x8];
3998 u8 table_id[0x18];
4000 u8 reserved_at_c0[0x18];
4001 u8 modify_enable_mask[0x8];
4003 u8 reserved_at_e0[0x20];
4005 u8 flow_index[0x20];
4007 u8 reserved_at_120[0xe0];
4013 u8 status[0x8];
4014 u8 reserved_at_8[0x18];
4016 u8 syndrome[0x20];
4018 u8 reserved_at_40[0x40];
4022 u8 opcode[0x10];
4023 u8 uid[0x10];
4025 u8 reserved_at_20[0x10];
4026 u8 op_mod[0x10];
4028 u8 reserved_at_40[0x8];
4029 u8 qpn[0x18];
4031 u8 reserved_at_60[0x20];
4033 u8 opt_param_mask[0x20];
4035 u8 reserved_at_a0[0x20];
4039 u8 reserved_at_800[0x80];
4043 u8 status[0x8];
4044 u8 reserved_at_8[0x18];
4046 u8 syndrome[0x20];
4048 u8 reserved_at_40[0x40];
4052 u8 opcode[0x10];
4053 u8 uid[0x10];
4055 u8 reserved_at_20[0x10];
4056 u8 op_mod[0x10];
4058 u8 reserved_at_40[0x8];
4059 u8 qpn[0x18];
4061 u8 reserved_at_60[0x20];
4063 u8 opt_param_mask[0x20];
4065 u8 reserved_at_a0[0x20];
4069 u8 reserved_at_800[0x80];
4073 u8 status[0x8];
4074 u8 reserved_at_8[0x18];
4076 u8 syndrome[0x20];
4078 u8 reserved_at_40[0x40];
4082 u8 opcode[0x10];
4083 u8 uid[0x10];
4085 u8 reserved_at_20[0x10];
4086 u8 op_mod[0x10];
4088 u8 reserved_at_40[0x8];
4089 u8 qpn[0x18];
4091 u8 reserved_at_60[0x20];
4093 u8 opt_param_mask[0x20];
4095 u8 reserved_at_a0[0x20];
4099 u8 reserved_at_800[0x80];
4103 u8 status[0x8];
4104 u8 reserved_at_8[0x18];
4106 u8 syndrome[0x20];
4108 u8 reserved_at_40[0x40];
4114 u8 opcode[0x10];
4115 u8 reserved_at_10[0x10];
4117 u8 reserved_at_20[0x10];
4118 u8 op_mod[0x10];
4120 u8 reserved_at_40[0x8];
4121 u8 xrqn[0x18];
4123 u8 reserved_at_60[0x20];
4127 u8 status[0x8];
4128 u8 reserved_at_8[0x18];
4130 u8 syndrome[0x20];
4132 u8 reserved_at_40[0x40];
4136 u8 reserved_at_280[0x600];
4138 u8 pas[0][0x40];
4142 u8 opcode[0x10];
4143 u8 reserved_at_10[0x10];
4145 u8 reserved_at_20[0x10];
4146 u8 op_mod[0x10];
4148 u8 reserved_at_40[0x8];
4149 u8 xrc_srqn[0x18];
4151 u8 reserved_at_60[0x20];
4155 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
4156 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
4160 u8 status[0x8];
4161 u8 reserved_at_8[0x18];
4163 u8 syndrome[0x20];
4165 u8 reserved_at_40[0x20];
4167 u8 reserved_at_60[0x18];
4168 u8 admin_state[0x4];
4169 u8 state[0x4];
4173 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
4174 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
4178 u8 opcode[0x10];
4179 u8 uid[0x10];
4181 u8 reserved_at_20[0x10];
4182 u8 op_mod[0x10];
4184 u8 reserved_at_40[0x20];
4186 u8 reserved_at_60[0x20];
4190 u8 status[0x8];
4191 u8 reserved_at_8[0x18];
4193 u8 syndrome[0x20];
4195 u8 reserved_at_40[0x40];
4199 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
4200 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4204 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
4205 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
4206 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
4207 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4208 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
4209 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
4213 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
4217 u8 reserved_at_0[0x4];
4218 u8 type[0x4];
4219 u8 reserved_at_8[0x8];
4220 u8 counter[0x10];
4222 u8 counter_group_id[0x20];
4231 u8 opcode[0x10];
4232 u8 uid[0x10];
4234 u8 reserved_at_20[0x10];
4235 u8 op_mod[0x10];
4237 u8 reserved_at_40[0x10];
4238 u8 num_of_counters[0x10];
4240 u8 reserved_at_60[0x20];
4246 u8 status[0x8];
4247 u8 reserved_at_8[0x18];
4249 u8 syndrome[0x20];
4251 u8 reserved_at_40[0x40];
4255 u8 opcode[0x10];
4256 u8 reserved_at_10[0x10];
4258 u8 reserved_at_20[0x10];
4259 u8 op_mod[0x10];
4261 u8 other_vport[0x1];
4262 u8 reserved_at_41[0xf];
4263 u8 vport_number[0x10];
4265 u8 reserved_at_60[0x20];
4269 u8 status[0x8];
4270 u8 reserved_at_8[0x18];
4272 u8 syndrome[0x20];
4274 u8 reserved_at_40[0x40];
4280 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
4284 u8 opcode[0x10];
4285 u8 reserved_at_10[0x10];
4287 u8 reserved_at_20[0x10];
4288 u8 op_mod[0x10];
4290 u8 other_vport[0x1];
4291 u8 reserved_at_41[0xf];
4292 u8 vport_number[0x10];
4294 u8 reserved_at_60[0x20];
4298 u8 status[0x8];
4299 u8 reserved_at_8[0x18];
4301 u8 syndrome[0x20];
4303 u8 reserved_at_40[0x40];
4329 u8 reserved_at_680[0xa00];
4333 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
4337 u8 opcode[0x10];
4338 u8 reserved_at_10[0x10];
4340 u8 reserved_at_20[0x10];
4341 u8 op_mod[0x10];
4343 u8 other_vport[0x1];
4344 u8 reserved_at_41[0xb];
4345 u8 port_num[0x4];
4346 u8 vport_number[0x10];
4348 u8 reserved_at_60[0x60];
4350 u8 clear[0x1];
4351 u8 reserved_at_c1[0x1f];
4353 u8 reserved_at_e0[0x20];
4357 u8 status[0x8];
4358 u8 reserved_at_8[0x18];
4360 u8 syndrome[0x20];
4362 u8 reserved_at_40[0x40];
4368 u8 opcode[0x10];
4369 u8 reserved_at_10[0x10];
4371 u8 reserved_at_20[0x10];
4372 u8 op_mod[0x10];
4374 u8 reserved_at_40[0x8];
4375 u8 tisn[0x18];
4377 u8 reserved_at_60[0x20];
4381 u8 status[0x8];
4382 u8 reserved_at_8[0x18];
4384 u8 syndrome[0x20];
4386 u8 reserved_at_40[0xc0];
4392 u8 opcode[0x10];
4393 u8 reserved_at_10[0x10];
4395 u8 reserved_at_20[0x10];
4396 u8 op_mod[0x10];
4398 u8 reserved_at_40[0x8];
4399 u8 tirn[0x18];
4401 u8 reserved_at_60[0x20];
4405 u8 status[0x8];
4406 u8 reserved_at_8[0x18];
4408 u8 syndrome[0x20];
4410 u8 reserved_at_40[0x40];
4414 u8 reserved_at_280[0x600];
4416 u8 pas[0][0x40];
4420 u8 opcode[0x10];
4421 u8 reserved_at_10[0x10];
4423 u8 reserved_at_20[0x10];
4424 u8 op_mod[0x10];
4426 u8 reserved_at_40[0x8];
4427 u8 srqn[0x18];
4429 u8 reserved_at_60[0x20];
4433 u8 status[0x8];
4434 u8 reserved_at_8[0x18];
4436 u8 syndrome[0x20];
4438 u8 reserved_at_40[0xc0];
4444 u8 opcode[0x10];
4445 u8 reserved_at_10[0x10];
4447 u8 reserved_at_20[0x10];
4448 u8 op_mod[0x10];
4450 u8 reserved_at_40[0x8];
4451 u8 sqn[0x18];
4453 u8 reserved_at_60[0x20];
4457 u8 status[0x8];
4458 u8 reserved_at_8[0x18];
4460 u8 syndrome[0x20];
4462 u8 dump_fill_mkey[0x20];
4464 u8 resd_lkey[0x20];
4466 u8 null_mkey[0x20];
4468 u8 reserved_at_a0[0x60];
4472 u8 opcode[0x10];
4473 u8 reserved_at_10[0x10];
4475 u8 reserved_at_20[0x10];
4476 u8 op_mod[0x10];
4478 u8 reserved_at_40[0x40];
4482 u8 opcode[0x10];
4483 u8 reserved_at_10[0x10];
4485 u8 reserved_at_20[0x10];
4486 u8 op_mod[0x10];
4488 u8 reserved_at_40[0xc0];
4492 u8 reserved_at_300[0x100];
4496 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4500 u8 opcode[0x10];
4501 u8 reserved_at_10[0x10];
4503 u8 reserved_at_20[0x10];
4504 u8 op_mod[0x10];
4506 u8 scheduling_hierarchy[0x8];
4507 u8 reserved_at_48[0x18];
4509 u8 scheduling_element_id[0x20];
4511 u8 reserved_at_80[0x180];
4515 u8 status[0x8];
4516 u8 reserved_at_8[0x18];
4518 u8 syndrome[0x20];
4520 u8 reserved_at_40[0xc0];
4526 u8 opcode[0x10];
4527 u8 reserved_at_10[0x10];
4529 u8 reserved_at_20[0x10];
4530 u8 op_mod[0x10];
4532 u8 reserved_at_40[0x8];
4533 u8 rqtn[0x18];
4535 u8 reserved_at_60[0x20];
4539 u8 status[0x8];
4540 u8 reserved_at_8[0x18];
4542 u8 syndrome[0x20];
4544 u8 reserved_at_40[0xc0];
4550 u8 opcode[0x10];
4551 u8 reserved_at_10[0x10];
4553 u8 reserved_at_20[0x10];
4554 u8 op_mod[0x10];
4556 u8 reserved_at_40[0x8];
4557 u8 rqn[0x18];
4559 u8 reserved_at_60[0x20];
4563 u8 status[0x8];
4564 u8 reserved_at_8[0x18];
4566 u8 syndrome[0x20];
4568 u8 reserved_at_40[0x40];
4574 u8 opcode[0x10];
4575 u8 reserved_at_10[0x10];
4577 u8 reserved_at_20[0x10];
4578 u8 op_mod[0x10];
4580 u8 roce_address_index[0x10];
4581 u8 reserved_at_50[0xc];
4582 u8 vhca_port_num[0x4];
4584 u8 reserved_at_60[0x20];
4588 u8 status[0x8];
4589 u8 reserved_at_8[0x18];
4591 u8 syndrome[0x20];
4593 u8 reserved_at_40[0xc0];
4599 u8 opcode[0x10];
4600 u8 reserved_at_10[0x10];
4602 u8 reserved_at_20[0x10];
4603 u8 op_mod[0x10];
4605 u8 reserved_at_40[0x8];
4606 u8 rmpn[0x18];
4608 u8 reserved_at_60[0x20];
4612 u8 status[0x8];
4613 u8 reserved_at_8[0x18];
4615 u8 syndrome[0x20];
4617 u8 reserved_at_40[0x40];
4619 u8 opt_param_mask[0x20];
4621 u8 reserved_at_a0[0x20];
4625 u8 reserved_at_800[0x80];
4627 u8 pas[0][0x40];
4631 u8 opcode[0x10];
4632 u8 reserved_at_10[0x10];
4634 u8 reserved_at_20[0x10];
4635 u8 op_mod[0x10];
4637 u8 reserved_at_40[0x8];
4638 u8 qpn[0x18];
4640 u8 reserved_at_60[0x20];
4644 u8 status[0x8];
4645 u8 reserved_at_8[0x18];
4647 u8 syndrome[0x20];
4649 u8 reserved_at_40[0x40];
4651 u8 rx_write_requests[0x20];
4653 u8 reserved_at_a0[0x20];
4655 u8 rx_read_requests[0x20];
4657 u8 reserved_at_e0[0x20];
4659 u8 rx_atomic_requests[0x20];
4661 u8 reserved_at_120[0x20];
4663 u8 rx_dct_connect[0x20];
4665 u8 reserved_at_160[0x20];
4667 u8 out_of_buffer[0x20];
4669 u8 reserved_at_1a0[0x20];
4671 u8 out_of_sequence[0x20];
4673 u8 reserved_at_1e0[0x20];
4675 u8 duplicate_request[0x20];
4677 u8 reserved_at_220[0x20];
4679 u8 rnr_nak_retry_err[0x20];
4681 u8 reserved_at_260[0x20];
4683 u8 packet_seq_err[0x20];
4685 u8 reserved_at_2a0[0x20];
4687 u8 implied_nak_seq_err[0x20];
4689 u8 reserved_at_2e0[0x20];
4691 u8 local_ack_timeout_err[0x20];
4693 u8 reserved_at_320[0xa0];
4695 u8 resp_local_length_error[0x20];
4697 u8 req_local_length_error[0x20];
4699 u8 resp_local_qp_error[0x20];
4701 u8 local_operation_error[0x20];
4703 u8 resp_local_protection[0x20];
4705 u8 req_local_protection[0x20];
4707 u8 resp_cqe_error[0x20];
4709 u8 req_cqe_error[0x20];
4711 u8 req_mw_binding[0x20];
4713 u8 req_bad_response[0x20];
4715 u8 req_remote_invalid_request[0x20];
4717 u8 resp_remote_invalid_request[0x20];
4719 u8 req_remote_access_errors[0x20];
4721 u8 resp_remote_access_errors[0x20];
4723 u8 req_remote_operation_errors[0x20];
4725 u8 req_transport_retries_exceeded[0x20];
4727 u8 cq_overflow[0x20];
4729 u8 resp_cqe_flush_error[0x20];
4731 u8 req_cqe_flush_error[0x20];
4733 u8 reserved_at_620[0x1e0];
4737 u8 opcode[0x10];
4738 u8 reserved_at_10[0x10];
4740 u8 reserved_at_20[0x10];
4741 u8 op_mod[0x10];
4743 u8 reserved_at_40[0x80];
4745 u8 clear[0x1];
4746 u8 reserved_at_c1[0x1f];
4748 u8 reserved_at_e0[0x18];
4749 u8 counter_set_id[0x8];
4753 u8 status[0x8];
4754 u8 reserved_at_8[0x18];
4756 u8 syndrome[0x20];
4758 u8 embedded_cpu_function[0x1];
4759 u8 reserved_at_41[0xf];
4760 u8 function_id[0x10];
4762 u8 num_pages[0x20];
4766 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4767 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4768 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4772 u8 opcode[0x10];
4773 u8 reserved_at_10[0x10];
4775 u8 reserved_at_20[0x10];
4776 u8 op_mod[0x10];
4778 u8 embedded_cpu_function[0x1];
4779 u8 reserved_at_41[0xf];
4780 u8 function_id[0x10];
4782 u8 reserved_at_60[0x20];
4786 u8 status[0x8];
4787 u8 reserved_at_8[0x18];
4789 u8 syndrome[0x20];
4791 u8 reserved_at_40[0x40];
4797 u8 opcode[0x10];
4798 u8 reserved_at_10[0x10];
4800 u8 reserved_at_20[0x10];
4801 u8 op_mod[0x10];
4803 u8 other_vport[0x1];
4804 u8 reserved_at_41[0xf];
4805 u8 vport_number[0x10];
4807 u8 reserved_at_60[0x5];
4808 u8 allowed_list_type[0x3];
4809 u8 reserved_at_68[0x18];
4813 u8 status[0x8];
4814 u8 reserved_at_8[0x18];
4816 u8 syndrome[0x20];
4818 u8 reserved_at_40[0x40];
4822 u8 reserved_at_280[0x600];
4824 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4826 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4830 u8 opcode[0x10];
4831 u8 reserved_at_10[0x10];
4833 u8 reserved_at_20[0x10];
4834 u8 op_mod[0x10];
4836 u8 reserved_at_40[0x8];
4837 u8 mkey_index[0x18];
4839 u8 pg_access[0x1];
4840 u8 reserved_at_61[0x1f];
4844 u8 status[0x8];
4845 u8 reserved_at_8[0x18];
4847 u8 syndrome[0x20];
4849 u8 reserved_at_40[0x40];
4851 u8 mad_dumux_parameters_block[0x20];
4855 u8 opcode[0x10];
4856 u8 reserved_at_10[0x10];
4858 u8 reserved_at_20[0x10];
4859 u8 op_mod[0x10];
4861 u8 reserved_at_40[0x40];
4865 u8 status[0x8];
4866 u8 reserved_at_8[0x18];
4868 u8 syndrome[0x20];
4870 u8 reserved_at_40[0xa0];
4872 u8 reserved_at_e0[0x13];
4873 u8 vlan_valid[0x1];
4874 u8 vlan[0xc];
4878 u8 reserved_at_140[0xc0];
4882 u8 opcode[0x10];
4883 u8 reserved_at_10[0x10];
4885 u8 reserved_at_20[0x10];
4886 u8 op_mod[0x10];
4888 u8 reserved_at_40[0x60];
4890 u8 reserved_at_a0[0x8];
4891 u8 table_index[0x18];
4893 u8 reserved_at_c0[0x140];
4897 u8 status[0x8];
4898 u8 reserved_at_8[0x18];
4900 u8 syndrome[0x20];
4902 u8 reserved_at_40[0x10];
4903 u8 current_issi[0x10];
4905 u8 reserved_at_60[0xa0];
4907 u8 reserved_at_100[76][0x8];
4908 u8 supported_issi_dw0[0x20];
4912 u8 opcode[0x10];
4913 u8 reserved_at_10[0x10];
4915 u8 reserved_at_20[0x10];
4916 u8 op_mod[0x10];
4918 u8 reserved_at_40[0x40];
4922 u8 status[0x8];
4923 u8 reserved_0[0x18];
4925 u8 syndrome[0x20];
4926 u8 reserved_1[0x40];
4930 u8 opcode[0x10];
4931 u8 reserved_0[0x10];
4933 u8 reserved_1[0x10];
4934 u8 op_mod[0x10];
4936 u8 reserved_2[0x40];
4937 u8 driver_version[64][0x8];
4941 u8 status[0x8];
4942 u8 reserved_at_8[0x18];
4944 u8 syndrome[0x20];
4946 u8 reserved_at_40[0x40];
4948 struct mlx5_ifc_pkey_bits pkey[0];
4952 u8 opcode[0x10];
4953 u8 reserved_at_10[0x10];
4955 u8 reserved_at_20[0x10];
4956 u8 op_mod[0x10];
4958 u8 other_vport[0x1];
4959 u8 reserved_at_41[0xb];
4960 u8 port_num[0x4];
4961 u8 vport_number[0x10];
4963 u8 reserved_at_60[0x10];
4964 u8 pkey_index[0x10];
4968 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4974 u8 status[0x8];
4975 u8 reserved_at_8[0x18];
4977 u8 syndrome[0x20];
4979 u8 reserved_at_40[0x20];
4981 u8 gids_num[0x10];
4982 u8 reserved_at_70[0x10];
4984 struct mlx5_ifc_array128_auto_bits gid[0];
4988 u8 opcode[0x10];
4989 u8 reserved_at_10[0x10];
4991 u8 reserved_at_20[0x10];
4992 u8 op_mod[0x10];
4994 u8 other_vport[0x1];
4995 u8 reserved_at_41[0xb];
4996 u8 port_num[0x4];
4997 u8 vport_number[0x10];
4999 u8 reserved_at_60[0x10];
5000 u8 gid_index[0x10];
5004 u8 status[0x8];
5005 u8 reserved_at_8[0x18];
5007 u8 syndrome[0x20];
5009 u8 reserved_at_40[0x40];
5015 u8 opcode[0x10];
5016 u8 reserved_at_10[0x10];
5018 u8 reserved_at_20[0x10];
5019 u8 op_mod[0x10];
5021 u8 other_vport[0x1];
5022 u8 reserved_at_41[0xb];
5023 u8 port_num[0x4];
5024 u8 vport_number[0x10];
5026 u8 reserved_at_60[0x20];
5030 u8 status[0x8];
5031 u8 reserved_at_8[0x18];
5033 u8 syndrome[0x20];
5035 u8 reserved_at_40[0x40];
5041 u8 opcode[0x10];
5042 u8 reserved_at_10[0x10];
5044 u8 reserved_at_20[0x10];
5045 u8 op_mod[0x10];
5047 u8 other_function[0x1];
5048 u8 reserved_at_41[0xf];
5049 u8 function_id[0x10];
5051 u8 reserved_at_60[0x20];
5055 u8 roce[0x1];
5056 u8 reserved_at_1[0x27f];
5060 u8 status[0x8];
5061 u8 reserved_at_8[0x18];
5063 u8 syndrome[0x20];
5065 u8 reserved_at_40[0x40];
5071 u8 opcode[0x10];
5072 u8 reserved_at_10[0x10];
5074 u8 reserved_at_20[0x10];
5075 u8 op_mod[0x10];
5077 u8 reserved_at_40[0x10];
5078 u8 function_id[0x10];
5080 u8 reserved_at_60[0x20];
5084 u8 status[0x8];
5085 u8 reserved_at_8[0x18];
5087 u8 syndrome[0x20];
5089 u8 reserved_at_40[0x40];
5093 u8 opcode[0x10];
5094 u8 reserved_at_10[0x10];
5096 u8 reserved_at_20[0x10];
5097 u8 op_mod[0x10];
5099 u8 reserved_at_40[0x10];
5100 u8 function_id[0x10];
5101 u8 field_select[0x20];
5107 u8 reformat_en[0x1];
5108 u8 decap_en[0x1];
5109 u8 sw_owner[0x1];
5110 u8 termination_table[0x1];
5111 u8 table_miss_action[0x4];
5112 u8 level[0x8];
5113 u8 reserved_at_10[0x8];
5114 u8 log_size[0x8];
5116 u8 reserved_at_20[0x8];
5117 u8 table_miss_id[0x18];
5119 u8 reserved_at_40[0x8];
5120 u8 lag_master_next_table_id[0x18];
5122 u8 reserved_at_60[0x60];
5124 u8 sw_owner_icm_root_1[0x40];
5126 u8 sw_owner_icm_root_0[0x40];
5131 u8 status[0x8];
5132 u8 reserved_at_8[0x18];
5134 u8 syndrome[0x20];
5136 u8 reserved_at_40[0x80];
5142 u8 opcode[0x10];
5143 u8 reserved_at_10[0x10];
5145 u8 reserved_at_20[0x10];
5146 u8 op_mod[0x10];
5148 u8 reserved_at_40[0x40];
5150 u8 table_type[0x8];
5151 u8 reserved_at_88[0x18];
5153 u8 reserved_at_a0[0x8];
5154 u8 table_id[0x18];
5156 u8 reserved_at_c0[0x140];
5160 u8 status[0x8];
5161 u8 reserved_at_8[0x18];
5163 u8 syndrome[0x20];
5165 u8 reserved_at_40[0x1c0];
5171 u8 opcode[0x10];
5172 u8 reserved_at_10[0x10];
5174 u8 reserved_at_20[0x10];
5175 u8 op_mod[0x10];
5177 u8 reserved_at_40[0x40];
5179 u8 table_type[0x8];
5180 u8 reserved_at_88[0x18];
5182 u8 reserved_at_a0[0x8];
5183 u8 table_id[0x18];
5185 u8 reserved_at_c0[0x40];
5187 u8 flow_index[0x20];
5189 u8 reserved_at_120[0xe0];
5193 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5194 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5195 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5196 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
5197 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
5201 u8 status[0x8];
5202 u8 reserved_at_8[0x18];
5204 u8 syndrome[0x20];
5206 u8 reserved_at_40[0xa0];
5208 u8 start_flow_index[0x20];
5210 u8 reserved_at_100[0x20];
5212 u8 end_flow_index[0x20];
5214 u8 reserved_at_140[0xa0];
5216 u8 reserved_at_1e0[0x18];
5217 u8 match_criteria_enable[0x8];
5221 u8 reserved_at_1200[0xe00];
5225 u8 opcode[0x10];
5226 u8 reserved_at_10[0x10];
5228 u8 reserved_at_20[0x10];
5229 u8 op_mod[0x10];
5231 u8 reserved_at_40[0x40];
5233 u8 table_type[0x8];
5234 u8 reserved_at_88[0x18];
5236 u8 reserved_at_a0[0x8];
5237 u8 table_id[0x18];
5239 u8 group_id[0x20];
5241 u8 reserved_at_e0[0x120];
5245 u8 status[0x8];
5246 u8 reserved_at_8[0x18];
5248 u8 syndrome[0x20];
5250 u8 reserved_at_40[0x40];
5252 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
5256 u8 opcode[0x10];
5257 u8 reserved_at_10[0x10];
5259 u8 reserved_at_20[0x10];
5260 u8 op_mod[0x10];
5262 u8 reserved_at_40[0x80];
5264 u8 clear[0x1];
5265 u8 reserved_at_c1[0xf];
5266 u8 num_of_counters[0x10];
5268 u8 flow_counter_id[0x20];
5272 u8 status[0x8];
5273 u8 reserved_at_8[0x18];
5275 u8 syndrome[0x20];
5277 u8 reserved_at_40[0x40];
5283 u8 opcode[0x10];
5284 u8 reserved_at_10[0x10];
5286 u8 reserved_at_20[0x10];
5287 u8 op_mod[0x10];
5289 u8 other_vport[0x1];
5290 u8 reserved_at_41[0xf];
5291 u8 vport_number[0x10];
5293 u8 reserved_at_60[0x20];
5297 u8 status[0x8];
5298 u8 reserved_at_8[0x18];
5300 u8 syndrome[0x20];
5302 u8 reserved_at_40[0x40];
5306 u8 reserved_at_0[0x1b];
5307 u8 fdb_to_vport_reg_c_id[0x1];
5308 u8 vport_cvlan_insert[0x1];
5309 u8 vport_svlan_insert[0x1];
5310 u8 vport_cvlan_strip[0x1];
5311 u8 vport_svlan_strip[0x1];
5315 u8 opcode[0x10];
5316 u8 reserved_at_10[0x10];
5318 u8 reserved_at_20[0x10];
5319 u8 op_mod[0x10];
5321 u8 other_vport[0x1];
5322 u8 reserved_at_41[0xf];
5323 u8 vport_number[0x10];
5331 u8 status[0x8];
5332 u8 reserved_at_8[0x18];
5334 u8 syndrome[0x20];
5336 u8 reserved_at_40[0x40];
5340 u8 reserved_at_280[0x40];
5342 u8 event_bitmask[0x40];
5344 u8 reserved_at_300[0x580];
5346 u8 pas[0][0x40];
5350 u8 opcode[0x10];
5351 u8 reserved_at_10[0x10];
5353 u8 reserved_at_20[0x10];
5354 u8 op_mod[0x10];
5356 u8 reserved_at_40[0x18];
5357 u8 eq_number[0x8];
5359 u8 reserved_at_60[0x20];
5363 u8 reserved_at_0[0x5];
5364 u8 reformat_type[0x3];
5365 u8 reserved_at_8[0xe];
5366 u8 reformat_data_size[0xa];
5368 u8 reserved_at_20[0x10];
5369 u8 reformat_data[2][0x8];
5371 u8 more_reformat_data[0][0x8];
5375 u8 status[0x8];
5376 u8 reserved_at_8[0x18];
5378 u8 syndrome[0x20];
5380 u8 reserved_at_40[0xa0];
5382 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
5386 u8 opcode[0x10];
5387 u8 reserved_at_10[0x10];
5389 u8 reserved_at_20[0x10];
5390 u8 op_mod[0x10];
5392 u8 packet_reformat_id[0x20];
5394 u8 reserved_at_60[0xa0];
5398 u8 status[0x8];
5399 u8 reserved_at_8[0x18];
5401 u8 syndrome[0x20];
5403 u8 packet_reformat_id[0x20];
5405 u8 reserved_at_60[0x20];
5409 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5410 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5411 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5412 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5413 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5417 u8 opcode[0x10];
5418 u8 reserved_at_10[0x10];
5420 u8 reserved_at_20[0x10];
5421 u8 op_mod[0x10];
5423 u8 reserved_at_40[0xa0];
5429 u8 status[0x8];
5430 u8 reserved_at_8[0x18];
5432 u8 syndrome[0x20];
5434 u8 reserved_at_40[0x40];
5438 u8 opcode[0x10];
5439 u8 reserved_at_10[0x10];
5441 u8 reserved_20[0x10];
5442 u8 op_mod[0x10];
5444 u8 packet_reformat_id[0x20];
5446 u8 reserved_60[0x20];
5450 u8 action_type[0x4];
5451 u8 field[0xc];
5452 u8 reserved_at_10[0x3];
5453 u8 offset[0x5];
5454 u8 reserved_at_18[0x3];
5455 u8 length[0x5];
5457 u8 data[0x20];
5461 u8 action_type[0x4];
5462 u8 field[0xc];
5463 u8 reserved_at_10[0x10];
5465 u8 data[0x20];
5471 u8 reserved_at_0[0x40];
5475 MLX5_ACTION_TYPE_SET = 0x1,
5476 MLX5_ACTION_TYPE_ADD = 0x2,
5480 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
5481 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
5482 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
5483 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
5484 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
5485 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
5486 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
5487 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
5488 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
5489 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
5490 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
5491 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
5492 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
5493 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
5494 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
5495 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
5496 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
5497 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
5498 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
5499 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
5500 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
5501 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
5502 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
5503 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5504 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49,
5505 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50,
5506 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
5507 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52,
5508 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53,
5509 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
5510 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
5511 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
5512 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
5513 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
5517 u8 status[0x8];
5518 u8 reserved_at_8[0x18];
5520 u8 syndrome[0x20];
5522 u8 modify_header_id[0x20];
5524 u8 reserved_at_60[0x20];
5528 u8 opcode[0x10];
5529 u8 reserved_at_10[0x10];
5531 u8 reserved_at_20[0x10];
5532 u8 op_mod[0x10];
5534 u8 reserved_at_40[0x20];
5536 u8 table_type[0x8];
5537 u8 reserved_at_68[0x10];
5538 u8 num_of_actions[0x8];
5540 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
5544 u8 status[0x8];
5545 u8 reserved_at_8[0x18];
5547 u8 syndrome[0x20];
5549 u8 reserved_at_40[0x40];
5553 u8 opcode[0x10];
5554 u8 reserved_at_10[0x10];
5556 u8 reserved_at_20[0x10];
5557 u8 op_mod[0x10];
5559 u8 modify_header_id[0x20];
5561 u8 reserved_at_60[0x20];
5565 u8 status[0x8];
5566 u8 reserved_at_8[0x18];
5568 u8 syndrome[0x20];
5570 u8 reserved_at_40[0x40];
5574 u8 reserved_at_280[0x180];
5578 u8 opcode[0x10];
5579 u8 reserved_at_10[0x10];
5581 u8 reserved_at_20[0x10];
5582 u8 op_mod[0x10];
5584 u8 reserved_at_40[0x8];
5585 u8 dctn[0x18];
5587 u8 reserved_at_60[0x20];
5591 u8 status[0x8];
5592 u8 reserved_at_8[0x18];
5594 u8 syndrome[0x20];
5596 u8 reserved_at_40[0x40];
5600 u8 reserved_at_280[0x600];
5602 u8 pas[0][0x40];
5606 u8 opcode[0x10];
5607 u8 reserved_at_10[0x10];
5609 u8 reserved_at_20[0x10];
5610 u8 op_mod[0x10];
5612 u8 reserved_at_40[0x8];
5613 u8 cqn[0x18];
5615 u8 reserved_at_60[0x20];
5619 u8 status[0x8];
5620 u8 reserved_at_8[0x18];
5622 u8 syndrome[0x20];
5624 u8 reserved_at_40[0x20];
5626 u8 enable[0x1];
5627 u8 tag_enable[0x1];
5628 u8 reserved_at_62[0x1e];
5632 u8 opcode[0x10];
5633 u8 reserved_at_10[0x10];
5635 u8 reserved_at_20[0x10];
5636 u8 op_mod[0x10];
5638 u8 reserved_at_40[0x18];
5639 u8 priority[0x4];
5640 u8 cong_protocol[0x4];
5642 u8 reserved_at_60[0x20];
5646 u8 status[0x8];
5647 u8 reserved_at_8[0x18];
5649 u8 syndrome[0x20];
5651 u8 reserved_at_40[0x40];
5653 u8 rp_cur_flows[0x20];
5655 u8 sum_flows[0x20];
5657 u8 rp_cnp_ignored_high[0x20];
5659 u8 rp_cnp_ignored_low[0x20];
5661 u8 rp_cnp_handled_high[0x20];
5663 u8 rp_cnp_handled_low[0x20];
5665 u8 reserved_at_140[0x100];
5667 u8 time_stamp_high[0x20];
5669 u8 time_stamp_low[0x20];
5671 u8 accumulators_period[0x20];
5673 u8 np_ecn_marked_roce_packets_high[0x20];
5675 u8 np_ecn_marked_roce_packets_low[0x20];
5677 u8 np_cnp_sent_high[0x20];
5679 u8 np_cnp_sent_low[0x20];
5681 u8 reserved_at_320[0x560];
5685 u8 opcode[0x10];
5686 u8 reserved_at_10[0x10];
5688 u8 reserved_at_20[0x10];
5689 u8 op_mod[0x10];
5691 u8 clear[0x1];
5692 u8 reserved_at_41[0x1f];
5694 u8 reserved_at_60[0x20];
5698 u8 status[0x8];
5699 u8 reserved_at_8[0x18];
5701 u8 syndrome[0x20];
5703 u8 reserved_at_40[0x40];
5709 u8 opcode[0x10];
5710 u8 reserved_at_10[0x10];
5712 u8 reserved_at_20[0x10];
5713 u8 op_mod[0x10];
5715 u8 reserved_at_40[0x1c];
5716 u8 cong_protocol[0x4];
5718 u8 reserved_at_60[0x20];
5722 u8 status[0x8];
5723 u8 reserved_at_8[0x18];
5725 u8 syndrome[0x20];
5727 u8 reserved_at_40[0x40];
5733 u8 opcode[0x10];
5734 u8 reserved_at_10[0x10];
5736 u8 reserved_at_20[0x10];
5737 u8 op_mod[0x10];
5739 u8 reserved_at_40[0x40];
5743 u8 status[0x8];
5744 u8 reserved_at_8[0x18];
5746 u8 syndrome[0x20];
5748 u8 reserved_at_40[0x40];
5752 u8 opcode[0x10];
5753 u8 uid[0x10];
5755 u8 reserved_at_20[0x10];
5756 u8 op_mod[0x10];
5758 u8 reserved_at_40[0x8];
5759 u8 qpn[0x18];
5761 u8 reserved_at_60[0x20];
5765 u8 status[0x8];
5766 u8 reserved_at_8[0x18];
5768 u8 syndrome[0x20];
5770 u8 reserved_at_40[0x40];
5774 u8 opcode[0x10];
5775 u8 uid[0x10];
5777 u8 reserved_at_20[0x10];
5778 u8 op_mod[0x10];
5780 u8 reserved_at_40[0x8];
5781 u8 qpn[0x18];
5783 u8 reserved_at_60[0x20];
5787 u8 status[0x8];
5788 u8 reserved_at_8[0x18];
5790 u8 syndrome[0x20];
5792 u8 reserved_at_40[0x40];
5796 u8 opcode[0x10];
5797 u8 reserved_at_10[0x10];
5799 u8 reserved_at_20[0x10];
5800 u8 op_mod[0x10];
5802 u8 error[0x1];
5803 u8 reserved_at_41[0x4];
5804 u8 page_fault_type[0x3];
5805 u8 wq_number[0x18];
5807 u8 reserved_at_60[0x8];
5808 u8 token[0x18];
5812 u8 status[0x8];
5813 u8 reserved_at_8[0x18];
5815 u8 syndrome[0x20];
5817 u8 reserved_at_40[0x40];
5821 u8 opcode[0x10];
5822 u8 reserved_at_10[0x10];
5824 u8 reserved_at_20[0x10];
5825 u8 op_mod[0x10];
5827 u8 reserved_at_40[0x40];
5831 u8 status[0x8];
5832 u8 reserved_at_8[0x18];
5834 u8 syndrome[0x20];
5836 u8 reserved_at_40[0x40];
5840 u8 opcode[0x10];
5841 u8 reserved_at_10[0x10];
5843 u8 reserved_at_20[0x10];
5844 u8 op_mod[0x10];
5846 u8 other_vport[0x1];
5847 u8 reserved_at_41[0xf];
5848 u8 vport_number[0x10];
5850 u8 reserved_at_60[0x18];
5851 u8 admin_state[0x4];
5852 u8 reserved_at_7c[0x4];
5856 u8 status[0x8];
5857 u8 reserved_at_8[0x18];
5859 u8 syndrome[0x20];
5861 u8 reserved_at_40[0x40];
5865 u8 reserved_at_0[0x20];
5867 u8 reserved_at_20[0x1d];
5868 u8 lag_tx_port_affinity[0x1];
5869 u8 strict_lag_tx_port_affinity[0x1];
5870 u8 prio[0x1];
5874 u8 opcode[0x10];
5875 u8 uid[0x10];
5877 u8 reserved_at_20[0x10];
5878 u8 op_mod[0x10];
5880 u8 reserved_at_40[0x8];
5881 u8 tisn[0x18];
5883 u8 reserved_at_60[0x20];
5887 u8 reserved_at_c0[0x40];
5893 u8 reserved_at_0[0x20];
5895 u8 reserved_at_20[0x1b];
5896 u8 self_lb_en[0x1];
5897 u8 reserved_at_3c[0x1];
5898 u8 hash[0x1];
5899 u8 reserved_at_3e[0x1];
5900 u8 lro[0x1];
5904 u8 status[0x8];
5905 u8 reserved_at_8[0x18];
5907 u8 syndrome[0x20];
5909 u8 reserved_at_40[0x40];
5913 u8 opcode[0x10];
5914 u8 uid[0x10];
5916 u8 reserved_at_20[0x10];
5917 u8 op_mod[0x10];
5919 u8 reserved_at_40[0x8];
5920 u8 tirn[0x18];
5922 u8 reserved_at_60[0x20];
5926 u8 reserved_at_c0[0x40];
5932 u8 status[0x8];
5933 u8 reserved_at_8[0x18];
5935 u8 syndrome[0x20];
5937 u8 reserved_at_40[0x40];
5941 u8 opcode[0x10];
5942 u8 uid[0x10];
5944 u8 reserved_at_20[0x10];
5945 u8 op_mod[0x10];
5947 u8 sq_state[0x4];
5948 u8 reserved_at_44[0x4];
5949 u8 sqn[0x18];
5951 u8 reserved_at_60[0x20];
5953 u8 modify_bitmask[0x40];
5955 u8 reserved_at_c0[0x40];
5961 u8 status[0x8];
5962 u8 reserved_at_8[0x18];
5964 u8 syndrome[0x20];
5966 u8 reserved_at_40[0x1c0];
5970 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5971 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5975 u8 opcode[0x10];
5976 u8 reserved_at_10[0x10];
5978 u8 reserved_at_20[0x10];
5979 u8 op_mod[0x10];
5981 u8 scheduling_hierarchy[0x8];
5982 u8 reserved_at_48[0x18];
5984 u8 scheduling_element_id[0x20];
5986 u8 reserved_at_80[0x20];
5988 u8 modify_bitmask[0x20];
5990 u8 reserved_at_c0[0x40];
5994 u8 reserved_at_300[0x100];
5998 u8 status[0x8];
5999 u8 reserved_at_8[0x18];
6001 u8 syndrome[0x20];
6003 u8 reserved_at_40[0x40];
6007 u8 reserved_at_0[0x20];
6009 u8 reserved_at_20[0x1f];
6010 u8 rqn_list[0x1];
6014 u8 opcode[0x10];
6015 u8 uid[0x10];
6017 u8 reserved_at_20[0x10];
6018 u8 op_mod[0x10];
6020 u8 reserved_at_40[0x8];
6021 u8 rqtn[0x18];
6023 u8 reserved_at_60[0x20];
6027 u8 reserved_at_c0[0x40];
6033 u8 status[0x8];
6034 u8 reserved_at_8[0x18];
6036 u8 syndrome[0x20];
6038 u8 reserved_at_40[0x40];
6048 u8 opcode[0x10];
6049 u8 uid[0x10];
6051 u8 reserved_at_20[0x10];
6052 u8 op_mod[0x10];
6054 u8 rq_state[0x4];
6055 u8 reserved_at_44[0x4];
6056 u8 rqn[0x18];
6058 u8 reserved_at_60[0x20];
6060 u8 modify_bitmask[0x40];
6062 u8 reserved_at_c0[0x40];
6068 u8 status[0x8];
6069 u8 reserved_at_8[0x18];
6071 u8 syndrome[0x20];
6073 u8 reserved_at_40[0x40];
6077 u8 reserved_at_0[0x20];
6079 u8 reserved_at_20[0x1f];
6080 u8 lwm[0x1];
6084 u8 opcode[0x10];
6085 u8 uid[0x10];
6087 u8 reserved_at_20[0x10];
6088 u8 op_mod[0x10];
6090 u8 rmp_state[0x4];
6091 u8 reserved_at_44[0x4];
6092 u8 rmpn[0x18];
6094 u8 reserved_at_60[0x20];
6098 u8 reserved_at_c0[0x40];
6104 u8 status[0x8];
6105 u8 reserved_at_8[0x18];
6107 u8 syndrome[0x20];
6109 u8 reserved_at_40[0x40];
6113 u8 reserved_at_0[0x12];
6114 u8 affiliation[0x1];
6115 u8 reserved_at_13[0x1];
6116 u8 disable_uc_local_lb[0x1];
6117 u8 disable_mc_local_lb[0x1];
6118 u8 node_guid[0x1];
6119 u8 port_guid[0x1];
6120 u8 min_inline[0x1];
6121 u8 mtu[0x1];
6122 u8 change_event[0x1];
6123 u8 promisc[0x1];
6124 u8 permanent_address[0x1];
6125 u8 addresses_list[0x1];
6126 u8 roce_en[0x1];
6127 u8 reserved_at_1f[0x1];
6131 u8 opcode[0x10];
6132 u8 reserved_at_10[0x10];
6134 u8 reserved_at_20[0x10];
6135 u8 op_mod[0x10];
6137 u8 other_vport[0x1];
6138 u8 reserved_at_41[0xf];
6139 u8 vport_number[0x10];
6143 u8 reserved_at_80[0x780];
6149 u8 status[0x8];
6150 u8 reserved_at_8[0x18];
6152 u8 syndrome[0x20];
6154 u8 reserved_at_40[0x40];
6158 u8 opcode[0x10];
6159 u8 reserved_at_10[0x10];
6161 u8 reserved_at_20[0x10];
6162 u8 op_mod[0x10];
6164 u8 other_vport[0x1];
6165 u8 reserved_at_41[0xb];
6166 u8 port_num[0x4];
6167 u8 vport_number[0x10];
6169 u8 reserved_at_60[0x20];
6175 u8 status[0x8];
6176 u8 reserved_at_8[0x18];
6178 u8 syndrome[0x20];
6180 u8 reserved_at_40[0x40];
6184 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
6185 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
6189 u8 opcode[0x10];
6190 u8 uid[0x10];
6192 u8 reserved_at_20[0x10];
6193 u8 op_mod[0x10];
6195 u8 reserved_at_40[0x8];
6196 u8 cqn[0x18];
6202 u8 reserved_at_280[0x60];
6204 u8 cq_umem_valid[0x1];
6205 u8 reserved_at_2e1[0x1f];
6207 u8 reserved_at_300[0x580];
6209 u8 pas[0][0x40];
6213 u8 status[0x8];
6214 u8 reserved_at_8[0x18];
6216 u8 syndrome[0x20];
6218 u8 reserved_at_40[0x40];
6222 u8 opcode[0x10];
6223 u8 reserved_at_10[0x10];
6225 u8 reserved_at_20[0x10];
6226 u8 op_mod[0x10];
6228 u8 reserved_at_40[0x18];
6229 u8 priority[0x4];
6230 u8 cong_protocol[0x4];
6232 u8 enable[0x1];
6233 u8 tag_enable[0x1];
6234 u8 reserved_at_62[0x1e];
6238 u8 status[0x8];
6239 u8 reserved_at_8[0x18];
6241 u8 syndrome[0x20];
6243 u8 reserved_at_40[0x40];
6247 u8 opcode[0x10];
6248 u8 reserved_at_10[0x10];
6250 u8 reserved_at_20[0x10];
6251 u8 op_mod[0x10];
6253 u8 reserved_at_40[0x1c];
6254 u8 cong_protocol[0x4];
6258 u8 reserved_at_80[0x80];
6264 u8 status[0x8];
6265 u8 reserved_at_8[0x18];
6267 u8 syndrome[0x20];
6269 u8 output_num_entries[0x20];
6271 u8 reserved_at_60[0x20];
6273 u8 pas[0][0x40];
6277 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
6278 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
6279 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
6283 u8 opcode[0x10];
6284 u8 reserved_at_10[0x10];
6286 u8 reserved_at_20[0x10];
6287 u8 op_mod[0x10];
6289 u8 embedded_cpu_function[0x1];
6290 u8 reserved_at_41[0xf];
6291 u8 function_id[0x10];
6293 u8 input_num_entries[0x20];
6295 u8 pas[0][0x40];
6299 u8 status[0x8];
6300 u8 reserved_at_8[0x18];
6302 u8 syndrome[0x20];
6304 u8 reserved_at_40[0x40];
6306 u8 response_mad_packet[256][0x8];
6310 u8 opcode[0x10];
6311 u8 reserved_at_10[0x10];
6313 u8 reserved_at_20[0x10];
6314 u8 op_mod[0x10];
6316 u8 remote_lid[0x10];
6317 u8 reserved_at_50[0x8];
6318 u8 port[0x8];
6320 u8 reserved_at_60[0x20];
6322 u8 mad[256][0x8];
6326 u8 status[0x8];
6327 u8 reserved_at_8[0x18];
6329 u8 syndrome[0x20];
6331 u8 reserved_at_40[0x40];
6335 u8 opcode[0x10];
6336 u8 reserved_at_10[0x10];
6338 u8 reserved_at_20[0x10];
6339 u8 op_mod[0x10];
6341 u8 reserved_at_40[0x40];
6342 u8 sw_owner_id[4][0x20];
6346 u8 status[0x8];
6347 u8 reserved_at_8[0x18];
6349 u8 syndrome[0x20];
6351 u8 reserved_at_40[0x40];
6355 u8 opcode[0x10];
6356 u8 uid[0x10];
6358 u8 reserved_at_20[0x10];
6359 u8 op_mod[0x10];
6361 u8 reserved_at_40[0x8];
6362 u8 qpn[0x18];
6364 u8 reserved_at_60[0x20];
6366 u8 opt_param_mask[0x20];
6368 u8 reserved_at_a0[0x20];
6372 u8 reserved_at_800[0x80];
6376 u8 status[0x8];
6377 u8 reserved_at_8[0x18];
6379 u8 syndrome[0x20];
6381 u8 reserved_at_40[0x40];
6385 u8 opcode[0x10];
6386 u8 uid[0x10];
6388 u8 reserved_at_20[0x10];
6389 u8 op_mod[0x10];
6391 u8 reserved_at_40[0x8];
6392 u8 qpn[0x18];
6394 u8 reserved_at_60[0x20];
6396 u8 opt_param_mask[0x20];
6398 u8 reserved_at_a0[0x20];
6402 u8 reserved_at_800[0x80];
6406 u8 status[0x8];
6407 u8 reserved_at_8[0x18];
6409 u8 syndrome[0x20];
6411 u8 reserved_at_40[0x40];
6413 u8 packet_headers_log[128][0x8];
6415 u8 packet_syndrome[64][0x8];
6419 u8 opcode[0x10];
6420 u8 reserved_at_10[0x10];
6422 u8 reserved_at_20[0x10];
6423 u8 op_mod[0x10];
6425 u8 reserved_at_40[0x40];
6429 u8 opcode[0x10];
6430 u8 reserved_at_10[0x10];
6432 u8 reserved_at_20[0x10];
6433 u8 op_mod[0x10];
6435 u8 reserved_at_40[0x18];
6436 u8 eq_number[0x8];
6438 u8 reserved_at_60[0x20];
6440 u8 eqe[64][0x8];
6444 u8 status[0x8];
6445 u8 reserved_at_8[0x18];
6447 u8 syndrome[0x20];
6449 u8 reserved_at_40[0x40];
6453 u8 status[0x8];
6454 u8 reserved_at_8[0x18];
6456 u8 syndrome[0x20];
6458 u8 reserved_at_40[0x20];
6462 u8 opcode[0x10];
6463 u8 reserved_at_10[0x10];
6465 u8 reserved_at_20[0x10];
6466 u8 op_mod[0x10];
6468 u8 embedded_cpu_function[0x1];
6469 u8 reserved_at_41[0xf];
6470 u8 function_id[0x10];
6472 u8 reserved_at_60[0x20];
6476 u8 status[0x8];
6477 u8 reserved_at_8[0x18];
6479 u8 syndrome[0x20];
6481 u8 reserved_at_40[0x40];
6485 u8 opcode[0x10];
6486 u8 uid[0x10];
6488 u8 reserved_at_20[0x10];
6489 u8 op_mod[0x10];
6491 u8 reserved_at_40[0x8];
6492 u8 dctn[0x18];
6494 u8 reserved_at_60[0x20];
6498 u8 status[0x8];
6499 u8 reserved_at_8[0x18];
6501 u8 syndrome[0x20];
6503 u8 reserved_at_40[0x20];
6507 u8 opcode[0x10];
6508 u8 reserved_at_10[0x10];
6510 u8 reserved_at_20[0x10];
6511 u8 op_mod[0x10];
6513 u8 embedded_cpu_function[0x1];
6514 u8 reserved_at_41[0xf];
6515 u8 function_id[0x10];
6517 u8 reserved_at_60[0x20];
6521 u8 status[0x8];
6522 u8 reserved_at_8[0x18];
6524 u8 syndrome[0x20];
6526 u8 reserved_at_40[0x40];
6530 u8 opcode[0x10];
6531 u8 uid[0x10];
6533 u8 reserved_at_20[0x10];
6534 u8 op_mod[0x10];
6536 u8 reserved_at_40[0x8];
6537 u8 qpn[0x18];
6539 u8 reserved_at_60[0x20];
6541 u8 multicast_gid[16][0x8];
6545 u8 status[0x8];
6546 u8 reserved_at_8[0x18];
6548 u8 syndrome[0x20];
6550 u8 reserved_at_40[0x40];
6554 u8 opcode[0x10];
6555 u8 uid[0x10];
6557 u8 reserved_at_20[0x10];
6558 u8 op_mod[0x10];
6560 u8 reserved_at_40[0x8];
6561 u8 xrqn[0x18];
6563 u8 reserved_at_60[0x20];
6567 u8 status[0x8];
6568 u8 reserved_at_8[0x18];
6570 u8 syndrome[0x20];
6572 u8 reserved_at_40[0x40];
6576 u8 opcode[0x10];
6577 u8 uid[0x10];
6579 u8 reserved_at_20[0x10];
6580 u8 op_mod[0x10];
6582 u8 reserved_at_40[0x8];
6583 u8 xrc_srqn[0x18];
6585 u8 reserved_at_60[0x20];
6589 u8 status[0x8];
6590 u8 reserved_at_8[0x18];
6592 u8 syndrome[0x20];
6594 u8 reserved_at_40[0x40];
6598 u8 opcode[0x10];
6599 u8 uid[0x10];
6601 u8 reserved_at_20[0x10];
6602 u8 op_mod[0x10];
6604 u8 reserved_at_40[0x8];
6605 u8 tisn[0x18];
6607 u8 reserved_at_60[0x20];
6611 u8 status[0x8];
6612 u8 reserved_at_8[0x18];
6614 u8 syndrome[0x20];
6616 u8 reserved_at_40[0x40];
6620 u8 opcode[0x10];
6621 u8 uid[0x10];
6623 u8 reserved_at_20[0x10];
6624 u8 op_mod[0x10];
6626 u8 reserved_at_40[0x8];
6627 u8 tirn[0x18];
6629 u8 reserved_at_60[0x20];
6633 u8 status[0x8];
6634 u8 reserved_at_8[0x18];
6636 u8 syndrome[0x20];
6638 u8 reserved_at_40[0x40];
6642 u8 opcode[0x10];
6643 u8 uid[0x10];
6645 u8 reserved_at_20[0x10];
6646 u8 op_mod[0x10];
6648 u8 reserved_at_40[0x8];
6649 u8 srqn[0x18];
6651 u8 reserved_at_60[0x20];
6655 u8 status[0x8];
6656 u8 reserved_at_8[0x18];
6658 u8 syndrome[0x20];
6660 u8 reserved_at_40[0x40];
6664 u8 opcode[0x10];
6665 u8 uid[0x10];
6667 u8 reserved_at_20[0x10];
6668 u8 op_mod[0x10];
6670 u8 reserved_at_40[0x8];
6671 u8 sqn[0x18];
6673 u8 reserved_at_60[0x20];
6677 u8 status[0x8];
6678 u8 reserved_at_8[0x18];
6680 u8 syndrome[0x20];
6682 u8 reserved_at_40[0x1c0];
6686 u8 opcode[0x10];
6687 u8 reserved_at_10[0x10];
6689 u8 reserved_at_20[0x10];
6690 u8 op_mod[0x10];
6692 u8 scheduling_hierarchy[0x8];
6693 u8 reserved_at_48[0x18];
6695 u8 scheduling_element_id[0x20];
6697 u8 reserved_at_80[0x180];
6701 u8 status[0x8];
6702 u8 reserved_at_8[0x18];
6704 u8 syndrome[0x20];
6706 u8 reserved_at_40[0x40];
6710 u8 opcode[0x10];
6711 u8 uid[0x10];
6713 u8 reserved_at_20[0x10];
6714 u8 op_mod[0x10];
6716 u8 reserved_at_40[0x8];
6717 u8 rqtn[0x18];
6719 u8 reserved_at_60[0x20];
6723 u8 status[0x8];
6724 u8 reserved_at_8[0x18];
6726 u8 syndrome[0x20];
6728 u8 reserved_at_40[0x40];
6732 u8 opcode[0x10];
6733 u8 uid[0x10];
6735 u8 reserved_at_20[0x10];
6736 u8 op_mod[0x10];
6738 u8 reserved_at_40[0x8];
6739 u8 rqn[0x18];
6741 u8 reserved_at_60[0x20];
6745 u8 opcode[0x10];
6746 u8 reserved_at_10[0x10];
6748 u8 reserved_at_20[0x10];
6749 u8 op_mod[0x10];
6751 u8 reserved_at_40[0x20];
6753 u8 reserved_at_60[0x10];
6754 u8 delay_drop_timeout[0x10];
6758 u8 status[0x8];
6759 u8 reserved_at_8[0x18];
6761 u8 syndrome[0x20];
6763 u8 reserved_at_40[0x40];
6767 u8 status[0x8];
6768 u8 reserved_at_8[0x18];
6770 u8 syndrome[0x20];
6772 u8 reserved_at_40[0x40];
6776 u8 opcode[0x10];
6777 u8 uid[0x10];
6779 u8 reserved_at_20[0x10];
6780 u8 op_mod[0x10];
6782 u8 reserved_at_40[0x8];
6783 u8 rmpn[0x18];
6785 u8 reserved_at_60[0x20];
6789 u8 status[0x8];
6790 u8 reserved_at_8[0x18];
6792 u8 syndrome[0x20];
6794 u8 reserved_at_40[0x40];
6798 u8 opcode[0x10];
6799 u8 uid[0x10];
6801 u8 reserved_at_20[0x10];
6802 u8 op_mod[0x10];
6804 u8 reserved_at_40[0x8];
6805 u8 qpn[0x18];
6807 u8 reserved_at_60[0x20];
6811 u8 status[0x8];
6812 u8 reserved_at_8[0x18];
6814 u8 syndrome[0x20];
6816 u8 reserved_at_40[0x40];
6820 u8 opcode[0x10];
6821 u8 reserved_at_10[0x10];
6823 u8 reserved_at_20[0x10];
6824 u8 op_mod[0x10];
6826 u8 reserved_at_40[0x8];
6827 u8 psvn[0x18];
6829 u8 reserved_at_60[0x20];
6833 u8 status[0x8];
6834 u8 reserved_at_8[0x18];
6836 u8 syndrome[0x20];
6838 u8 reserved_at_40[0x40];
6842 u8 opcode[0x10];
6843 u8 reserved_at_10[0x10];
6845 u8 reserved_at_20[0x10];
6846 u8 op_mod[0x10];
6848 u8 reserved_at_40[0x8];
6849 u8 mkey_index[0x18];
6851 u8 reserved_at_60[0x20];
6855 u8 status[0x8];
6856 u8 reserved_at_8[0x18];
6858 u8 syndrome[0x20];
6860 u8 reserved_at_40[0x40];
6864 u8 opcode[0x10];
6865 u8 reserved_at_10[0x10];
6867 u8 reserved_at_20[0x10];
6868 u8 op_mod[0x10];
6870 u8 other_vport[0x1];
6871 u8 reserved_at_41[0xf];
6872 u8 vport_number[0x10];
6874 u8 reserved_at_60[0x20];
6876 u8 table_type[0x8];
6877 u8 reserved_at_88[0x18];
6879 u8 reserved_at_a0[0x8];
6880 u8 table_id[0x18];
6882 u8 reserved_at_c0[0x140];
6886 u8 status[0x8];
6887 u8 reserved_at_8[0x18];
6889 u8 syndrome[0x20];
6891 u8 reserved_at_40[0x40];
6895 u8 opcode[0x10];
6896 u8 reserved_at_10[0x10];
6898 u8 reserved_at_20[0x10];
6899 u8 op_mod[0x10];
6901 u8 other_vport[0x1];
6902 u8 reserved_at_41[0xf];
6903 u8 vport_number[0x10];
6905 u8 reserved_at_60[0x20];
6907 u8 table_type[0x8];
6908 u8 reserved_at_88[0x18];
6910 u8 reserved_at_a0[0x8];
6911 u8 table_id[0x18];
6913 u8 group_id[0x20];
6915 u8 reserved_at_e0[0x120];
6919 u8 status[0x8];
6920 u8 reserved_at_8[0x18];
6922 u8 syndrome[0x20];
6924 u8 reserved_at_40[0x40];
6928 u8 opcode[0x10];
6929 u8 reserved_at_10[0x10];
6931 u8 reserved_at_20[0x10];
6932 u8 op_mod[0x10];
6934 u8 reserved_at_40[0x18];
6935 u8 eq_number[0x8];
6937 u8 reserved_at_60[0x20];
6941 u8 status[0x8];
6942 u8 reserved_at_8[0x18];
6944 u8 syndrome[0x20];
6946 u8 reserved_at_40[0x40];
6950 u8 opcode[0x10];
6951 u8 uid[0x10];
6953 u8 reserved_at_20[0x10];
6954 u8 op_mod[0x10];
6956 u8 reserved_at_40[0x8];
6957 u8 dctn[0x18];
6959 u8 reserved_at_60[0x20];
6963 u8 status[0x8];
6964 u8 reserved_at_8[0x18];
6966 u8 syndrome[0x20];
6968 u8 reserved_at_40[0x40];
6972 u8 opcode[0x10];
6973 u8 uid[0x10];
6975 u8 reserved_at_20[0x10];
6976 u8 op_mod[0x10];
6978 u8 reserved_at_40[0x8];
6979 u8 cqn[0x18];
6981 u8 reserved_at_60[0x20];
6985 u8 status[0x8];
6986 u8 reserved_at_8[0x18];
6988 u8 syndrome[0x20];
6990 u8 reserved_at_40[0x40];
6994 u8 opcode[0x10];
6995 u8 reserved_at_10[0x10];
6997 u8 reserved_at_20[0x10];
6998 u8 op_mod[0x10];
7000 u8 reserved_at_40[0x20];
7002 u8 reserved_at_60[0x10];
7003 u8 vxlan_udp_port[0x10];
7007 u8 status[0x8];
7008 u8 reserved_at_8[0x18];
7010 u8 syndrome[0x20];
7012 u8 reserved_at_40[0x40];
7016 u8 opcode[0x10];
7017 u8 reserved_at_10[0x10];
7019 u8 reserved_at_20[0x10];
7020 u8 op_mod[0x10];
7022 u8 reserved_at_40[0x60];
7024 u8 reserved_at_a0[0x8];
7025 u8 table_index[0x18];
7027 u8 reserved_at_c0[0x140];
7031 u8 status[0x8];
7032 u8 reserved_at_8[0x18];
7034 u8 syndrome[0x20];
7036 u8 reserved_at_40[0x40];
7040 u8 opcode[0x10];
7041 u8 reserved_at_10[0x10];
7043 u8 reserved_at_20[0x10];
7044 u8 op_mod[0x10];
7046 u8 other_vport[0x1];
7047 u8 reserved_at_41[0xf];
7048 u8 vport_number[0x10];
7050 u8 reserved_at_60[0x20];
7052 u8 table_type[0x8];
7053 u8 reserved_at_88[0x18];
7055 u8 reserved_at_a0[0x8];
7056 u8 table_id[0x18];
7058 u8 reserved_at_c0[0x40];
7060 u8 flow_index[0x20];
7062 u8 reserved_at_120[0xe0];
7066 u8 status[0x8];
7067 u8 reserved_at_8[0x18];
7069 u8 syndrome[0x20];
7071 u8 reserved_at_40[0x40];
7075 u8 opcode[0x10];
7076 u8 uid[0x10];
7078 u8 reserved_at_20[0x10];
7079 u8 op_mod[0x10];
7081 u8 reserved_at_40[0x8];
7082 u8 xrcd[0x18];
7084 u8 reserved_at_60[0x20];
7088 u8 status[0x8];
7089 u8 reserved_at_8[0x18];
7091 u8 syndrome[0x20];
7093 u8 reserved_at_40[0x40];
7097 u8 opcode[0x10];
7098 u8 reserved_at_10[0x10];
7100 u8 reserved_at_20[0x10];
7101 u8 op_mod[0x10];
7103 u8 reserved_at_40[0x8];
7104 u8 uar[0x18];
7106 u8 reserved_at_60[0x20];
7110 u8 status[0x8];
7111 u8 reserved_at_8[0x18];
7113 u8 syndrome[0x20];
7115 u8 reserved_at_40[0x40];
7119 u8 opcode[0x10];
7120 u8 uid[0x10];
7122 u8 reserved_at_20[0x10];
7123 u8 op_mod[0x10];
7125 u8 reserved_at_40[0x8];
7126 u8 transport_domain[0x18];
7128 u8 reserved_at_60[0x20];
7132 u8 status[0x8];
7133 u8 reserved_at_8[0x18];
7135 u8 syndrome[0x20];
7137 u8 reserved_at_40[0x40];
7141 u8 opcode[0x10];
7142 u8 reserved_at_10[0x10];
7144 u8 reserved_at_20[0x10];
7145 u8 op_mod[0x10];
7147 u8 reserved_at_40[0x18];
7148 u8 counter_set_id[0x8];
7150 u8 reserved_at_60[0x20];
7154 u8 status[0x8];
7155 u8 reserved_at_8[0x18];
7157 u8 syndrome[0x20];
7159 u8 reserved_at_40[0x40];
7163 u8 opcode[0x10];
7164 u8 uid[0x10];
7166 u8 reserved_at_20[0x10];
7167 u8 op_mod[0x10];
7169 u8 reserved_at_40[0x8];
7170 u8 pd[0x18];
7172 u8 reserved_at_60[0x20];
7176 u8 status[0x8];
7177 u8 reserved_at_8[0x18];
7179 u8 syndrome[0x20];
7181 u8 reserved_at_40[0x40];
7185 u8 opcode[0x10];
7186 u8 reserved_at_10[0x10];
7188 u8 reserved_at_20[0x10];
7189 u8 op_mod[0x10];
7191 u8 flow_counter_id[0x20];
7193 u8 reserved_at_60[0x20];
7197 u8 status[0x8];
7198 u8 reserved_at_8[0x18];
7200 u8 syndrome[0x20];
7202 u8 reserved_at_40[0x8];
7203 u8 xrqn[0x18];
7205 u8 reserved_at_60[0x20];
7209 u8 opcode[0x10];
7210 u8 uid[0x10];
7212 u8 reserved_at_20[0x10];
7213 u8 op_mod[0x10];
7215 u8 reserved_at_40[0x40];
7221 u8 status[0x8];
7222 u8 reserved_at_8[0x18];
7224 u8 syndrome[0x20];
7226 u8 reserved_at_40[0x8];
7227 u8 xrc_srqn[0x18];
7229 u8 reserved_at_60[0x20];
7233 u8 opcode[0x10];
7234 u8 uid[0x10];
7236 u8 reserved_at_20[0x10];
7237 u8 op_mod[0x10];
7239 u8 reserved_at_40[0x40];
7243 u8 reserved_at_280[0x60];
7245 u8 xrc_srq_umem_valid[0x1];
7246 u8 reserved_at_2e1[0x1f];
7248 u8 reserved_at_300[0x580];
7250 u8 pas[0][0x40];
7254 u8 status[0x8];
7255 u8 reserved_at_8[0x18];
7257 u8 syndrome[0x20];
7259 u8 reserved_at_40[0x8];
7260 u8 tisn[0x18];
7262 u8 reserved_at_60[0x20];
7266 u8 opcode[0x10];
7267 u8 uid[0x10];
7269 u8 reserved_at_20[0x10];
7270 u8 op_mod[0x10];
7272 u8 reserved_at_40[0xc0];
7278 u8 status[0x8];
7279 u8 icm_address_63_40[0x18];
7281 u8 syndrome[0x20];
7283 u8 icm_address_39_32[0x8];
7284 u8 tirn[0x18];
7286 u8 icm_address_31_0[0x20];
7290 u8 opcode[0x10];
7291 u8 uid[0x10];
7293 u8 reserved_at_20[0x10];
7294 u8 op_mod[0x10];
7296 u8 reserved_at_40[0xc0];
7302 u8 status[0x8];
7303 u8 reserved_at_8[0x18];
7305 u8 syndrome[0x20];
7307 u8 reserved_at_40[0x8];
7308 u8 srqn[0x18];
7310 u8 reserved_at_60[0x20];
7314 u8 opcode[0x10];
7315 u8 uid[0x10];
7317 u8 reserved_at_20[0x10];
7318 u8 op_mod[0x10];
7320 u8 reserved_at_40[0x40];
7324 u8 reserved_at_280[0x600];
7326 u8 pas[0][0x40];
7330 u8 status[0x8];
7331 u8 reserved_at_8[0x18];
7333 u8 syndrome[0x20];
7335 u8 reserved_at_40[0x8];
7336 u8 sqn[0x18];
7338 u8 reserved_at_60[0x20];
7342 u8 opcode[0x10];
7343 u8 uid[0x10];
7345 u8 reserved_at_20[0x10];
7346 u8 op_mod[0x10];
7348 u8 reserved_at_40[0xc0];
7354 u8 status[0x8];
7355 u8 reserved_at_8[0x18];
7357 u8 syndrome[0x20];
7359 u8 reserved_at_40[0x40];
7361 u8 scheduling_element_id[0x20];
7363 u8 reserved_at_a0[0x160];
7367 u8 opcode[0x10];
7368 u8 reserved_at_10[0x10];
7370 u8 reserved_at_20[0x10];
7371 u8 op_mod[0x10];
7373 u8 scheduling_hierarchy[0x8];
7374 u8 reserved_at_48[0x18];
7376 u8 reserved_at_60[0xa0];
7380 u8 reserved_at_300[0x100];
7384 u8 status[0x8];
7385 u8 reserved_at_8[0x18];
7387 u8 syndrome[0x20];
7389 u8 reserved_at_40[0x8];
7390 u8 rqtn[0x18];
7392 u8 reserved_at_60[0x20];
7396 u8 opcode[0x10];
7397 u8 uid[0x10];
7399 u8 reserved_at_20[0x10];
7400 u8 op_mod[0x10];
7402 u8 reserved_at_40[0xc0];
7408 u8 status[0x8];
7409 u8 reserved_at_8[0x18];
7411 u8 syndrome[0x20];
7413 u8 reserved_at_40[0x8];
7414 u8 rqn[0x18];
7416 u8 reserved_at_60[0x20];
7420 u8 opcode[0x10];
7421 u8 uid[0x10];
7423 u8 reserved_at_20[0x10];
7424 u8 op_mod[0x10];
7426 u8 reserved_at_40[0xc0];
7432 u8 status[0x8];
7433 u8 reserved_at_8[0x18];
7435 u8 syndrome[0x20];
7437 u8 reserved_at_40[0x8];
7438 u8 rmpn[0x18];
7440 u8 reserved_at_60[0x20];
7444 u8 opcode[0x10];
7445 u8 uid[0x10];
7447 u8 reserved_at_20[0x10];
7448 u8 op_mod[0x10];
7450 u8 reserved_at_40[0xc0];
7456 u8 status[0x8];
7457 u8 reserved_at_8[0x18];
7459 u8 syndrome[0x20];
7461 u8 reserved_at_40[0x8];
7462 u8 qpn[0x18];
7464 u8 reserved_at_60[0x20];
7468 u8 opcode[0x10];
7469 u8 uid[0x10];
7471 u8 reserved_at_20[0x10];
7472 u8 op_mod[0x10];
7474 u8 reserved_at_40[0x40];
7476 u8 opt_param_mask[0x20];
7478 u8 reserved_at_a0[0x20];
7482 u8 reserved_at_800[0x60];
7484 u8 wq_umem_valid[0x1];
7485 u8 reserved_at_861[0x1f];
7487 u8 pas[0][0x40];
7491 u8 status[0x8];
7492 u8 reserved_at_8[0x18];
7494 u8 syndrome[0x20];
7496 u8 reserved_at_40[0x40];
7498 u8 reserved_at_80[0x8];
7499 u8 psv0_index[0x18];
7501 u8 reserved_at_a0[0x8];
7502 u8 psv1_index[0x18];
7504 u8 reserved_at_c0[0x8];
7505 u8 psv2_index[0x18];
7507 u8 reserved_at_e0[0x8];
7508 u8 psv3_index[0x18];
7512 u8 opcode[0x10];
7513 u8 reserved_at_10[0x10];
7515 u8 reserved_at_20[0x10];
7516 u8 op_mod[0x10];
7518 u8 num_psv[0x4];
7519 u8 reserved_at_44[0x4];
7520 u8 pd[0x18];
7522 u8 reserved_at_60[0x20];
7526 u8 status[0x8];
7527 u8 reserved_at_8[0x18];
7529 u8 syndrome[0x20];
7531 u8 reserved_at_40[0x8];
7532 u8 mkey_index[0x18];
7534 u8 reserved_at_60[0x20];
7538 u8 opcode[0x10];
7539 u8 reserved_at_10[0x10];
7541 u8 reserved_at_20[0x10];
7542 u8 op_mod[0x10];
7544 u8 reserved_at_40[0x20];
7546 u8 pg_access[0x1];
7547 u8 mkey_umem_valid[0x1];
7548 u8 reserved_at_62[0x1e];
7552 u8 reserved_at_280[0x80];
7554 u8 translations_octword_actual_size[0x20];
7556 u8 reserved_at_320[0x560];
7558 u8 klm_pas_mtt[0][0x20];
7562 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0,
7563 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1,
7564 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2,
7565 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3,
7566 MLX5_FLOW_TABLE_TYPE_FDB = 0X4,
7567 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5,
7568 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6,
7572 u8 status[0x8];
7573 u8 icm_address_63_40[0x18];
7575 u8 syndrome[0x20];
7577 u8 icm_address_39_32[0x8];
7578 u8 table_id[0x18];
7580 u8 icm_address_31_0[0x20];
7584 u8 opcode[0x10];
7585 u8 reserved_at_10[0x10];
7587 u8 reserved_at_20[0x10];
7588 u8 op_mod[0x10];
7590 u8 other_vport[0x1];
7591 u8 reserved_at_41[0xf];
7592 u8 vport_number[0x10];
7594 u8 reserved_at_60[0x20];
7596 u8 table_type[0x8];
7597 u8 reserved_at_88[0x18];
7599 u8 reserved_at_a0[0x20];
7605 u8 status[0x8];
7606 u8 reserved_at_8[0x18];
7608 u8 syndrome[0x20];
7610 u8 reserved_at_40[0x8];
7611 u8 group_id[0x18];
7613 u8 reserved_at_60[0x20];
7617 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
7618 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
7619 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
7620 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7624 u8 opcode[0x10];
7625 u8 reserved_at_10[0x10];
7627 u8 reserved_at_20[0x10];
7628 u8 op_mod[0x10];
7630 u8 other_vport[0x1];
7631 u8 reserved_at_41[0xf];
7632 u8 vport_number[0x10];
7634 u8 reserved_at_60[0x20];
7636 u8 table_type[0x8];
7637 u8 reserved_at_88[0x18];
7639 u8 reserved_at_a0[0x8];
7640 u8 table_id[0x18];
7642 u8 source_eswitch_owner_vhca_id_valid[0x1];
7644 u8 reserved_at_c1[0x1f];
7646 u8 start_flow_index[0x20];
7648 u8 reserved_at_100[0x20];
7650 u8 end_flow_index[0x20];
7652 u8 reserved_at_140[0xa0];
7654 u8 reserved_at_1e0[0x18];
7655 u8 match_criteria_enable[0x8];
7659 u8 reserved_at_1200[0xe00];
7663 u8 status[0x8];
7664 u8 reserved_at_8[0x18];
7666 u8 syndrome[0x20];
7668 u8 reserved_at_40[0x18];
7669 u8 eq_number[0x8];
7671 u8 reserved_at_60[0x20];
7675 u8 opcode[0x10];
7676 u8 uid[0x10];
7678 u8 reserved_at_20[0x10];
7679 u8 op_mod[0x10];
7681 u8 reserved_at_40[0x40];
7685 u8 reserved_at_280[0x40];
7687 u8 event_bitmask[4][0x40];
7689 u8 reserved_at_3c0[0x4c0];
7691 u8 pas[0][0x40];
7695 u8 status[0x8];
7696 u8 reserved_at_8[0x18];
7698 u8 syndrome[0x20];
7700 u8 reserved_at_40[0x8];
7701 u8 dctn[0x18];
7703 u8 reserved_at_60[0x20];
7707 u8 opcode[0x10];
7708 u8 uid[0x10];
7710 u8 reserved_at_20[0x10];
7711 u8 op_mod[0x10];
7713 u8 reserved_at_40[0x40];
7717 u8 reserved_at_280[0x180];
7721 u8 status[0x8];
7722 u8 reserved_at_8[0x18];
7724 u8 syndrome[0x20];
7726 u8 reserved_at_40[0x8];
7727 u8 cqn[0x18];
7729 u8 reserved_at_60[0x20];
7733 u8 opcode[0x10];
7734 u8 uid[0x10];
7736 u8 reserved_at_20[0x10];
7737 u8 op_mod[0x10];
7739 u8 reserved_at_40[0x40];
7743 u8 reserved_at_280[0x60];
7745 u8 cq_umem_valid[0x1];
7746 u8 reserved_at_2e1[0x59f];
7748 u8 pas[0][0x40];
7752 u8 status[0x8];
7753 u8 reserved_at_8[0x18];
7755 u8 syndrome[0x20];
7757 u8 reserved_at_40[0x4];
7758 u8 min_delay[0xc];
7759 u8 int_vector[0x10];
7761 u8 reserved_at_60[0x20];
7765 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7766 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7770 u8 opcode[0x10];
7771 u8 reserved_at_10[0x10];
7773 u8 reserved_at_20[0x10];
7774 u8 op_mod[0x10];
7776 u8 reserved_at_40[0x4];
7777 u8 min_delay[0xc];
7778 u8 int_vector[0x10];
7780 u8 reserved_at_60[0x20];
7784 u8 status[0x8];
7785 u8 reserved_at_8[0x18];
7787 u8 syndrome[0x20];
7789 u8 reserved_at_40[0x40];
7793 u8 opcode[0x10];
7794 u8 uid[0x10];
7796 u8 reserved_at_20[0x10];
7797 u8 op_mod[0x10];
7799 u8 reserved_at_40[0x8];
7800 u8 qpn[0x18];
7802 u8 reserved_at_60[0x20];
7804 u8 multicast_gid[16][0x8];
7808 u8 status[0x8];
7809 u8 reserved_at_8[0x18];
7811 u8 syndrome[0x20];
7813 u8 reserved_at_40[0x40];
7817 u8 opcode[0x10];
7818 u8 reserved_at_10[0x10];
7820 u8 reserved_at_20[0x10];
7821 u8 op_mod[0x10];
7823 u8 reserved_at_40[0x8];
7824 u8 xrqn[0x18];
7826 u8 reserved_at_60[0x10];
7827 u8 lwm[0x10];
7831 u8 status[0x8];
7832 u8 reserved_at_8[0x18];
7834 u8 syndrome[0x20];
7836 u8 reserved_at_40[0x40];
7840 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7844 u8 opcode[0x10];
7845 u8 uid[0x10];
7847 u8 reserved_at_20[0x10];
7848 u8 op_mod[0x10];
7850 u8 reserved_at_40[0x8];
7851 u8 xrc_srqn[0x18];
7853 u8 reserved_at_60[0x10];
7854 u8 lwm[0x10];
7858 u8 status[0x8];
7859 u8 reserved_at_8[0x18];
7861 u8 syndrome[0x20];
7863 u8 reserved_at_40[0x40];
7867 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7868 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7872 u8 opcode[0x10];
7873 u8 uid[0x10];
7875 u8 reserved_at_20[0x10];
7876 u8 op_mod[0x10];
7878 u8 reserved_at_40[0x8];
7879 u8 srq_number[0x18];
7881 u8 reserved_at_60[0x10];
7882 u8 lwm[0x10];
7886 u8 status[0x8];
7887 u8 reserved_at_8[0x18];
7889 u8 syndrome[0x20];
7891 u8 reserved_at_40[0x40];
7895 u8 opcode[0x10];
7896 u8 reserved_at_10[0x10];
7898 u8 reserved_at_20[0x10];
7899 u8 op_mod[0x10];
7901 u8 reserved_at_40[0x8];
7902 u8 dct_number[0x18];
7904 u8 reserved_at_60[0x20];
7908 u8 status[0x8];
7909 u8 reserved_at_8[0x18];
7911 u8 syndrome[0x20];
7913 u8 reserved_at_40[0x8];
7914 u8 xrcd[0x18];
7916 u8 reserved_at_60[0x20];
7920 u8 opcode[0x10];
7921 u8 uid[0x10];
7923 u8 reserved_at_20[0x10];
7924 u8 op_mod[0x10];
7926 u8 reserved_at_40[0x40];
7930 u8 status[0x8];
7931 u8 reserved_at_8[0x18];
7933 u8 syndrome[0x20];
7935 u8 reserved_at_40[0x8];
7936 u8 uar[0x18];
7938 u8 reserved_at_60[0x20];
7942 u8 opcode[0x10];
7943 u8 reserved_at_10[0x10];
7945 u8 reserved_at_20[0x10];
7946 u8 op_mod[0x10];
7948 u8 reserved_at_40[0x40];
7952 u8 status[0x8];
7953 u8 reserved_at_8[0x18];
7955 u8 syndrome[0x20];
7957 u8 reserved_at_40[0x8];
7958 u8 transport_domain[0x18];
7960 u8 reserved_at_60[0x20];
7964 u8 opcode[0x10];
7965 u8 uid[0x10];
7967 u8 reserved_at_20[0x10];
7968 u8 op_mod[0x10];
7970 u8 reserved_at_40[0x40];
7974 u8 status[0x8];
7975 u8 reserved_at_8[0x18];
7977 u8 syndrome[0x20];
7979 u8 reserved_at_40[0x18];
7980 u8 counter_set_id[0x8];
7982 u8 reserved_at_60[0x20];
7986 u8 opcode[0x10];
7987 u8 uid[0x10];
7989 u8 reserved_at_20[0x10];
7990 u8 op_mod[0x10];
7992 u8 reserved_at_40[0x40];
7996 u8 status[0x8];
7997 u8 reserved_at_8[0x18];
7999 u8 syndrome[0x20];
8001 u8 reserved_at_40[0x8];
8002 u8 pd[0x18];
8004 u8 reserved_at_60[0x20];
8008 u8 opcode[0x10];
8009 u8 uid[0x10];
8011 u8 reserved_at_20[0x10];
8012 u8 op_mod[0x10];
8014 u8 reserved_at_40[0x40];
8018 u8 status[0x8];
8019 u8 reserved_at_8[0x18];
8021 u8 syndrome[0x20];
8023 u8 flow_counter_id[0x20];
8025 u8 reserved_at_60[0x20];
8029 u8 opcode[0x10];
8030 u8 reserved_at_10[0x10];
8032 u8 reserved_at_20[0x10];
8033 u8 op_mod[0x10];
8035 u8 reserved_at_40[0x38];
8036 u8 flow_counter_bulk[0x8];
8040 u8 status[0x8];
8041 u8 reserved_at_8[0x18];
8043 u8 syndrome[0x20];
8045 u8 reserved_at_40[0x40];
8049 u8 opcode[0x10];
8050 u8 reserved_at_10[0x10];
8052 u8 reserved_at_20[0x10];
8053 u8 op_mod[0x10];
8055 u8 reserved_at_40[0x20];
8057 u8 reserved_at_60[0x10];
8058 u8 vxlan_udp_port[0x10];
8062 u8 status[0x8];
8063 u8 reserved_at_8[0x18];
8065 u8 syndrome[0x20];
8067 u8 reserved_at_40[0x40];
8071 u8 opcode[0x10];
8072 u8 reserved_at_10[0x10];
8074 u8 reserved_at_20[0x10];
8075 u8 op_mod[0x10];
8077 u8 reserved_at_40[0x10];
8078 u8 rate_limit_index[0x10];
8080 u8 reserved_at_60[0x20];
8082 u8 rate_limit[0x20];
8084 u8 burst_upper_bound[0x20];
8086 u8 reserved_at_c0[0x10];
8087 u8 typical_packet_size[0x10];
8089 u8 reserved_at_e0[0x120];
8093 u8 status[0x8];
8094 u8 reserved_at_8[0x18];
8096 u8 syndrome[0x20];
8098 u8 reserved_at_40[0x40];
8100 u8 register_data[0][0x20];
8104 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
8105 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
8109 u8 opcode[0x10];
8110 u8 reserved_at_10[0x10];
8112 u8 reserved_at_20[0x10];
8113 u8 op_mod[0x10];
8115 u8 reserved_at_40[0x10];
8116 u8 register_id[0x10];
8118 u8 argument[0x20];
8120 u8 register_data[0][0x20];
8124 u8 status[0x4];
8125 u8 version[0x4];
8126 u8 local_port[0x8];
8127 u8 pnat[0x2];
8128 u8 reserved_at_12[0x2];
8129 u8 lane[0x4];
8130 u8 reserved_at_18[0x8];
8132 u8 reserved_at_20[0x20];
8134 u8 reserved_at_40[0x7];
8135 u8 polarity[0x1];
8136 u8 ob_tap0[0x8];
8137 u8 ob_tap1[0x8];
8138 u8 ob_tap2[0x8];
8140 u8 reserved_at_60[0xc];
8141 u8 ob_preemp_mode[0x4];
8142 u8 ob_reg[0x8];
8143 u8 ob_bias[0x8];
8145 u8 reserved_at_80[0x20];
8149 u8 status[0x4];
8150 u8 version[0x4];
8151 u8 local_port[0x8];
8152 u8 pnat[0x2];
8153 u8 reserved_at_12[0x2];
8154 u8 lane[0x4];
8155 u8 reserved_at_18[0x8];
8157 u8 time_to_link_up[0x10];
8158 u8 reserved_at_30[0xc];
8159 u8 grade_lane_speed[0x4];
8161 u8 grade_version[0x8];
8162 u8 grade[0x18];
8164 u8 reserved_at_60[0x4];
8165 u8 height_grade_type[0x4];
8166 u8 height_grade[0x18];
8168 u8 height_dz[0x10];
8169 u8 height_dv[0x10];
8171 u8 reserved_at_a0[0x10];
8172 u8 height_sigma[0x10];
8174 u8 reserved_at_c0[0x20];
8176 u8 reserved_at_e0[0x4];
8177 u8 phase_grade_type[0x4];
8178 u8 phase_grade[0x18];
8180 u8 reserved_at_100[0x8];
8181 u8 phase_eo_pos[0x8];
8182 u8 reserved_at_110[0x8];
8183 u8 phase_eo_neg[0x8];
8185 u8 ffe_set_tested[0x10];
8186 u8 test_errors_per_lane[0x10];
8190 u8 reserved_at_0[0x8];
8191 u8 local_port[0x8];
8192 u8 reserved_at_10[0x10];
8194 u8 reserved_at_20[0x1c];
8195 u8 vl_hw_cap[0x4];
8197 u8 reserved_at_40[0x1c];
8198 u8 vl_admin[0x4];
8200 u8 reserved_at_60[0x1c];
8201 u8 vl_operational[0x4];
8205 u8 swid[0x8];
8206 u8 local_port[0x8];
8207 u8 reserved_at_10[0x4];
8208 u8 admin_status[0x4];
8209 u8 reserved_at_18[0x4];
8210 u8 oper_status[0x4];
8212 u8 reserved_at_20[0x60];
8216 u8 reserved_at_0[0x1];
8217 u8 an_disable_admin[0x1];
8218 u8 an_disable_cap[0x1];
8219 u8 reserved_at_3[0x5];
8220 u8 local_port[0x8];
8221 u8 reserved_at_10[0xd];
8222 u8 proto_mask[0x3];
8224 u8 an_status[0x4];
8225 u8 reserved_at_24[0x1c];
8227 u8 ext_eth_proto_capability[0x20];
8229 u8 eth_proto_capability[0x20];
8231 u8 ib_link_width_capability[0x10];
8232 u8 ib_proto_capability[0x10];
8234 u8 ext_eth_proto_admin[0x20];
8236 u8 eth_proto_admin[0x20];
8238 u8 ib_link_width_admin[0x10];
8239 u8 ib_proto_admin[0x10];
8241 u8 ext_eth_proto_oper[0x20];
8243 u8 eth_proto_oper[0x20];
8245 u8 ib_link_width_oper[0x10];
8246 u8 ib_proto_oper[0x10];
8248 u8 reserved_at_160[0x1c];
8249 u8 connector_type[0x4];
8251 u8 eth_proto_lp_advertise[0x20];
8253 u8 reserved_at_1a0[0x60];
8257 u8 reserved_at_0[0x8];
8258 u8 local_port[0x8];
8259 u8 reserved_at_10[0x20];
8261 u8 beacon_duration[0x10];
8262 u8 reserved_at_40[0x10];
8264 u8 beacon_remain[0x10];
8268 u8 reserved_at_0[0x20];
8270 u8 algorithm_options[0x10];
8271 u8 reserved_at_30[0x4];
8272 u8 repetitions_mode[0x4];
8273 u8 num_of_repetitions[0x8];
8275 u8 grade_version[0x8];
8276 u8 height_grade_type[0x4];
8277 u8 phase_grade_type[0x4];
8278 u8 height_grade_weight[0x8];
8279 u8 phase_grade_weight[0x8];
8281 u8 gisim_measure_bits[0x10];
8282 u8 adaptive_tap_measure_bits[0x10];
8284 u8 ber_bath_high_error_threshold[0x10];
8285 u8 ber_bath_mid_error_threshold[0x10];
8287 u8 ber_bath_low_error_threshold[0x10];
8288 u8 one_ratio_high_threshold[0x10];
8290 u8 one_ratio_high_mid_threshold[0x10];
8291 u8 one_ratio_low_mid_threshold[0x10];
8293 u8 one_ratio_low_threshold[0x10];
8294 u8 ndeo_error_threshold[0x10];
8296 u8 mixer_offset_step_size[0x10];
8297 u8 reserved_at_110[0x8];
8298 u8 mix90_phase_for_voltage_bath[0x8];
8300 u8 mixer_offset_start[0x10];
8301 u8 mixer_offset_end[0x10];
8303 u8 reserved_at_140[0x15];
8304 u8 ber_test_time[0xb];
8308 u8 swid[0x8];
8309 u8 local_port[0x8];
8310 u8 sub_port[0x8];
8311 u8 reserved_at_18[0x8];
8313 u8 reserved_at_20[0x20];
8317 u8 reserved_at_0[0x8];
8318 u8 local_port[0x8];
8319 u8 reserved_at_10[0x5];
8320 u8 prio[0x3];
8321 u8 reserved_at_18[0x6];
8322 u8 mode[0x2];
8324 u8 reserved_at_20[0x20];
8326 u8 reserved_at_40[0x10];
8327 u8 min_threshold[0x10];
8329 u8 reserved_at_60[0x10];
8330 u8 max_threshold[0x10];
8332 u8 reserved_at_80[0x10];
8333 u8 mark_probability_denominator[0x10];
8335 u8 reserved_at_a0[0x60];
8339 u8 reserved_at_0[0x8];
8340 u8 local_port[0x8];
8341 u8 reserved_at_10[0x10];
8343 u8 reserved_at_20[0x60];
8345 u8 reserved_at_80[0x1c];
8346 u8 wrps_admin[0x4];
8348 u8 reserved_at_a0[0x1c];
8349 u8 wrps_status[0x4];
8351 u8 reserved_at_c0[0x8];
8352 u8 up_threshold[0x8];
8353 u8 reserved_at_d0[0x8];
8354 u8 down_threshold[0x8];
8356 u8 reserved_at_e0[0x20];
8358 u8 reserved_at_100[0x1c];
8359 u8 srps_admin[0x4];
8361 u8 reserved_at_120[0x1c];
8362 u8 srps_status[0x4];
8364 u8 reserved_at_140[0x40];
8368 u8 reserved_at_0[0x8];
8369 u8 local_port[0x8];
8370 u8 reserved_at_10[0x10];
8372 u8 reserved_at_20[0x8];
8373 u8 lb_cap[0x8];
8374 u8 reserved_at_30[0x8];
8375 u8 lb_en[0x8];
8379 u8 reserved_at_0[0x8];
8380 u8 local_port[0x8];
8381 u8 reserved_at_10[0x10];
8383 u8 reserved_at_20[0x20];
8385 u8 port_profile_mode[0x8];
8386 u8 static_port_profile[0x8];
8387 u8 active_port_profile[0x8];
8388 u8 reserved_at_58[0x8];
8390 u8 retransmission_active[0x8];
8391 u8 fec_mode_active[0x18];
8393 u8 rs_fec_correction_bypass_cap[0x4];
8394 u8 reserved_at_84[0x8];
8395 u8 fec_override_cap_56g[0x4];
8396 u8 fec_override_cap_100g[0x4];
8397 u8 fec_override_cap_50g[0x4];
8398 u8 fec_override_cap_25g[0x4];
8399 u8 fec_override_cap_10g_40g[0x4];
8401 u8 rs_fec_correction_bypass_admin[0x4];
8402 u8 reserved_at_a4[0x8];
8403 u8 fec_override_admin_56g[0x4];
8404 u8 fec_override_admin_100g[0x4];
8405 u8 fec_override_admin_50g[0x4];
8406 u8 fec_override_admin_25g[0x4];
8407 u8 fec_override_admin_10g_40g[0x4];
8411 u8 swid[0x8];
8412 u8 local_port[0x8];
8413 u8 pnat[0x2];
8414 u8 reserved_at_12[0x8];
8415 u8 grp[0x6];
8417 u8 clr[0x1];
8418 u8 reserved_at_21[0x1c];
8419 u8 prio_tc[0x3];
8425 u8 reserved_at_0[0x2];
8426 u8 depth[0x6];
8427 u8 pcie_index[0x8];
8428 u8 node[0x8];
8429 u8 reserved_at_18[0x8];
8431 u8 capability_mask[0x20];
8433 u8 reserved_at_40[0x8];
8434 u8 link_width_enabled[0x8];
8435 u8 link_speed_enabled[0x10];
8437 u8 lane0_physical_position[0x8];
8438 u8 link_width_active[0x8];
8439 u8 link_speed_active[0x10];
8441 u8 num_of_pfs[0x10];
8442 u8 num_of_vfs[0x10];
8444 u8 bdf0[0x10];
8445 u8 reserved_at_b0[0x10];
8447 u8 max_read_request_size[0x4];
8448 u8 max_payload_size[0x4];
8449 u8 reserved_at_c8[0x5];
8450 u8 pwr_status[0x3];
8451 u8 port_type[0x4];
8452 u8 reserved_at_d4[0xb];
8453 u8 lane_reversal[0x1];
8455 u8 reserved_at_e0[0x14];
8456 u8 pci_power[0xc];
8458 u8 reserved_at_100[0x20];
8460 u8 device_status[0x10];
8461 u8 port_state[0x8];
8462 u8 reserved_at_138[0x8];
8464 u8 reserved_at_140[0x10];
8465 u8 receiver_detect_result[0x10];
8467 u8 reserved_at_160[0x20];
8471 u8 reserved_at_0[0x8];
8472 u8 pcie_index[0x8];
8473 u8 reserved_at_10[0xa];
8474 u8 grp[0x6];
8476 u8 clr[0x1];
8477 u8 reserved_at_21[0x1f];
8483 u8 reserved_at_0[0x3];
8484 u8 single_mac[0x1];
8485 u8 reserved_at_4[0x4];
8486 u8 local_port[0x8];
8487 u8 mac_47_32[0x10];
8489 u8 mac_31_0[0x20];
8491 u8 reserved_at_40[0x40];
8495 u8 reserved_at_0[0x8];
8496 u8 local_port[0x8];
8497 u8 reserved_at_10[0x10];
8499 u8 max_mtu[0x10];
8500 u8 reserved_at_30[0x10];
8502 u8 admin_mtu[0x10];
8503 u8 reserved_at_50[0x10];
8505 u8 oper_mtu[0x10];
8506 u8 reserved_at_70[0x10];
8510 u8 reserved_at_0[0x8];
8511 u8 module[0x8];
8512 u8 reserved_at_10[0x10];
8514 u8 reserved_at_20[0x18];
8515 u8 attenuation_5g[0x8];
8517 u8 reserved_at_40[0x18];
8518 u8 attenuation_7g[0x8];
8520 u8 reserved_at_60[0x18];
8521 u8 attenuation_12g[0x8];
8525 u8 reserved_at_0[0x8];
8526 u8 module[0x8];
8527 u8 reserved_at_10[0xc];
8528 u8 module_status[0x4];
8530 u8 reserved_at_20[0x60];
8534 u8 module_state_updated[32][0x8];
8538 u8 reserved_at_0[0x4];
8539 u8 mlpn_status[0x4];
8540 u8 local_port[0x8];
8541 u8 reserved_at_10[0x10];
8543 u8 e[0x1];
8544 u8 reserved_at_21[0x1f];
8548 u8 rxtx[0x1];
8549 u8 reserved_at_1[0x7];
8550 u8 local_port[0x8];
8551 u8 reserved_at_10[0x8];
8552 u8 width[0x8];
8554 u8 lane0_module_mapping[0x20];
8556 u8 lane1_module_mapping[0x20];
8558 u8 lane2_module_mapping[0x20];
8560 u8 lane3_module_mapping[0x20];
8562 u8 reserved_at_a0[0x160];
8566 u8 reserved_at_0[0x8];
8567 u8 module[0x8];
8568 u8 reserved_at_10[0x4];
8569 u8 admin_status[0x4];
8570 u8 reserved_at_18[0x4];
8571 u8 oper_status[0x4];
8573 u8 ase[0x1];
8574 u8 ee[0x1];
8575 u8 reserved_at_22[0x1c];
8576 u8 e[0x2];
8578 u8 reserved_at_40[0x40];
8582 u8 reserved_at_0[0x4];
8583 u8 profile_id[0xc];
8584 u8 reserved_at_10[0x4];
8585 u8 proto_mask[0x4];
8586 u8 reserved_at_18[0x8];
8588 u8 reserved_at_20[0x10];
8589 u8 lane_speed[0x10];
8591 u8 reserved_at_40[0x17];
8592 u8 lpbf[0x1];
8593 u8 fec_mode_policy[0x8];
8595 u8 retransmission_capability[0x8];
8596 u8 fec_mode_capability[0x18];
8598 u8 retransmission_support_admin[0x8];
8599 u8 fec_mode_support_admin[0x18];
8601 u8 retransmission_request_admin[0x8];
8602 u8 fec_mode_request_admin[0x18];
8604 u8 reserved_at_c0[0x80];
8608 u8 reserved_at_0[0x8];
8609 u8 local_port[0x8];
8610 u8 reserved_at_10[0x8];
8611 u8 ib_port[0x8];
8613 u8 reserved_at_20[0x60];
8617 u8 reserved_at_0[0x8];
8618 u8 local_port[0x8];
8619 u8 reserved_at_10[0xd];
8620 u8 lbf_mode[0x3];
8622 u8 reserved_at_20[0x20];
8626 u8 reserved_at_0[0x8];
8627 u8 local_port[0x8];
8628 u8 reserved_at_10[0x10];
8630 u8 dic[0x1];
8631 u8 reserved_at_21[0x19];
8632 u8 ipg[0x4];
8633 u8 reserved_at_3e[0x2];
8637 u8 reserved_at_0[0x8];
8638 u8 local_port[0x8];
8639 u8 reserved_at_10[0x10];
8641 u8 reserved_at_20[0xe0];
8643 u8 port_filter[8][0x20];
8645 u8 port_filter_update_en[8][0x20];
8649 u8 reserved_at_0[0x8];
8650 u8 local_port[0x8];
8651 u8 reserved_at_10[0xb];
8652 u8 ppan_mask_n[0x1];
8653 u8 minor_stall_mask[0x1];
8654 u8 critical_stall_mask[0x1];
8655 u8 reserved_at_1e[0x2];
8657 u8 ppan[0x4];
8658 u8 reserved_at_24[0x4];
8659 u8 prio_mask_tx[0x8];
8660 u8 reserved_at_30[0x8];
8661 u8 prio_mask_rx[0x8];
8663 u8 pptx[0x1];
8664 u8 aptx[0x1];
8665 u8 pptx_mask_n[0x1];
8666 u8 reserved_at_43[0x5];
8667 u8 pfctx[0x8];
8668 u8 reserved_at_50[0x10];
8670 u8 pprx[0x1];
8671 u8 aprx[0x1];
8672 u8 pprx_mask_n[0x1];
8673 u8 reserved_at_63[0x5];
8674 u8 pfcrx[0x8];
8675 u8 reserved_at_70[0x10];
8677 u8 device_stall_minor_watermark[0x10];
8678 u8 device_stall_critical_watermark[0x10];
8680 u8 reserved_at_a0[0x60];
8684 u8 op[0x4];
8685 u8 reserved_at_4[0x4];
8686 u8 local_port[0x8];
8687 u8 reserved_at_10[0x10];
8689 u8 op_admin[0x8];
8690 u8 op_capability[0x8];
8691 u8 op_request[0x8];
8692 u8 op_active[0x8];
8694 u8 admin[0x40];
8696 u8 capability[0x40];
8698 u8 request[0x40];
8700 u8 active[0x40];
8702 u8 reserved_at_140[0x80];
8706 u8 reserved_at_0[0x8];
8707 u8 local_port[0x8];
8708 u8 reserved_at_10[0x10];
8710 u8 reserved_at_20[0xc];
8711 u8 error_count[0x4];
8712 u8 reserved_at_30[0x10];
8714 u8 reserved_at_40[0xc];
8715 u8 lane[0x4];
8716 u8 reserved_at_50[0x8];
8717 u8 error_type[0x8];
8721 u8 reserved_at_0[0x30];
8722 u8 field_select[0x10];
8724 u8 tx_overflow_sense[0x1];
8725 u8 mark_cqe[0x1];
8726 u8 mark_cnp[0x1];
8727 u8 reserved_at_43[0x1b];
8728 u8 tx_lossy_overflow_oper[0x2];
8730 u8 reserved_at_60[0x100];
8734 u8 reserved_at_0[0x6d];
8735 u8 rx_icrc_encapsulated_counter[0x1];
8736 u8 reserved_at_6e[0x4];
8737 u8 ptys_extended_ethernet[0x1];
8738 u8 reserved_at_73[0x3];
8739 u8 pfcc_mask[0x1];
8740 u8 reserved_at_77[0x3];
8741 u8 per_lane_error_counters[0x1];
8742 u8 rx_buffer_fullness_counters[0x1];
8743 u8 ptys_connector_type[0x1];
8744 u8 reserved_at_7d[0x1];
8745 u8 ppcnt_discard_group[0x1];
8746 u8 ppcnt_statistical_group[0x1];
8750 u8 port_access_reg_cap_mask_127_to_96[0x20];
8751 u8 port_access_reg_cap_mask_95_to_64[0x20];
8753 u8 port_access_reg_cap_mask_63_to_36[0x1c];
8754 u8 pplm[0x1];
8755 u8 port_access_reg_cap_mask_34_to_32[0x3];
8757 u8 port_access_reg_cap_mask_31_to_13[0x13];
8758 u8 pbmc[0x1];
8759 u8 pptb[0x1];
8760 u8 port_access_reg_cap_mask_10_to_09[0x2];
8761 u8 ppcnt[0x1];
8762 u8 port_access_reg_cap_mask_07_to_00[0x8];
8766 u8 reserved_at_0[0x8];
8767 u8 feature_group[0x8];
8768 u8 reserved_at_10[0x8];
8769 u8 access_reg_group[0x8];
8771 u8 reserved_at_20[0x20];
8775 u8 reserved_at_0[0x80];
8778 u8 reserved_at_c0[0x80];
8782 u8 reserved_at_0[0x80];
8785 u8 reserved_at_1c0[0xc0];
8789 u8 reserved_at_0[0x6e];
8790 u8 pci_status_and_power[0x1];
8791 u8 reserved_at_6f[0x5];
8792 u8 mark_tx_action_cnp[0x1];
8793 u8 mark_tx_action_cqe[0x1];
8794 u8 dynamic_tx_overflow[0x1];
8795 u8 reserved_at_77[0x4];
8796 u8 pcie_outbound_stalled[0x1];
8797 u8 tx_overflow_buffer_pkt[0x1];
8798 u8 mtpps_enh_out_per_adj[0x1];
8799 u8 mtpps_fs[0x1];
8800 u8 pcie_performance_group[0x1];
8804 u8 reserved_at_0[0x1c];
8805 u8 mcda[0x1];
8806 u8 mcc[0x1];
8807 u8 mcqi[0x1];
8808 u8 mcqs[0x1];
8810 u8 regs_95_to_87[0x9];
8811 u8 mpegc[0x1];
8812 u8 regs_85_to_68[0x12];
8813 u8 tracer_registers[0x4];
8815 u8 regs_63_to_32[0x20];
8816 u8 regs_31_to_0[0x20];
8820 u8 reserved_at_0[0x8];
8821 u8 feature_group[0x8];
8822 u8 reserved_at_10[0x8];
8823 u8 access_reg_group[0x8];
8825 u8 reserved_at_20[0x20];
8829 u8 reserved_at_0[0x80];
8832 u8 reserved_at_c0[0x80];
8836 u8 reserved_at_0[0x80];
8839 u8 reserved_at_1c0[0x80];
8843 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
8844 u8 qpdpm[0x1];
8845 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
8846 u8 qdpm[0x1];
8847 u8 qpts[0x1];
8848 u8 qcap[0x1];
8849 u8 qcam_access_reg_cap_mask_0[0x1];
8853 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
8854 u8 qpts_trust_both[0x1];
8858 u8 reserved_at_0[0x8];
8859 u8 feature_group[0x8];
8860 u8 reserved_at_10[0x8];
8861 u8 access_reg_group[0x8];
8862 u8 reserved_at_20[0x20];
8866 u8 reserved_at_0[0x80];
8869 u8 reserved_at_c0[0x80];
8873 u8 reserved_at_0[0x80];
8876 u8 reserved_at_1c0[0x80];
8880 u8 reserved_at_0[0x18];
8881 u8 core_dump_type[0x8];
8883 u8 reserved_at_20[0x30];
8884 u8 vhca_id[0x10];
8886 u8 reserved_at_60[0x8];
8887 u8 qpn[0x18];
8888 u8 reserved_at_80[0x180];
8892 u8 reserved_at_0[0x8];
8893 u8 local_port[0x8];
8894 u8 reserved_at_10[0x10];
8896 u8 port_capability_mask[4][0x20];
8900 u8 swid[0x8];
8901 u8 local_port[0x8];
8902 u8 reserved_at_10[0x4];
8903 u8 admin_status[0x4];
8904 u8 reserved_at_18[0x4];
8905 u8 oper_status[0x4];
8907 u8 ase[0x1];
8908 u8 ee[0x1];
8909 u8 reserved_at_22[0x1c];
8910 u8 e[0x2];
8912 u8 reserved_at_40[0x40];
8916 u8 reserved_at_0[0x8];
8917 u8 opamp_group[0x8];
8918 u8 reserved_at_10[0xc];
8919 u8 opamp_group_type[0x4];
8921 u8 start_index[0x10];
8922 u8 reserved_at_30[0x4];
8923 u8 num_of_indices[0xc];
8925 u8 index_data[18][0x10];
8929 u8 reserved_at_0[0x8];
8930 u8 local_port[0x8];
8931 u8 reserved_at_10[0x10];
8932 u8 entropy_force_cap[0x1];
8933 u8 entropy_calc_cap[0x1];
8934 u8 entropy_gre_calc_cap[0x1];
8935 u8 reserved_at_23[0x1b];
8936 u8 fcs_cap[0x1];
8937 u8 reserved_at_3f[0x1];
8938 u8 entropy_force[0x1];
8939 u8 entropy_calc[0x1];
8940 u8 entropy_gre_calc[0x1];
8941 u8 reserved_at_43[0x1b];
8942 u8 fcs_chk[0x1];
8943 u8 reserved_at_5f[0x1];
8947 u8 reserved_at_0[0x6];
8948 u8 rx_lane[0x2];
8949 u8 reserved_at_8[0x6];
8950 u8 tx_lane[0x2];
8951 u8 reserved_at_10[0x8];
8952 u8 module[0x8];
8956 u8 reserved_at_0[0x6];
8957 u8 lossy[0x1];
8958 u8 epsb[0x1];
8959 u8 reserved_at_8[0xc];
8960 u8 size[0xc];
8962 u8 xoff_threshold[0x10];
8963 u8 xon_threshold[0x10];
8967 u8 node_description[64][0x8];
8971 u8 reserved_at_0[0x18];
8972 u8 power_settings_level[0x8];
8974 u8 reserved_at_20[0x60];
8978 u8 he[0x1];
8979 u8 reserved_at_1[0x1f];
8981 u8 reserved_at_20[0x60];
8985 u8 reserved_at_0[0x20];
8987 u8 mkey[0x20];
8989 u8 addressh_63_32[0x20];
8991 u8 addressl_31_0[0x20];
8995 u8 dc_key[0x40];
8997 u8 ext[0x1];
8998 u8 reserved_at_41[0x7];
8999 u8 destination_qp_dct[0x18];
9001 u8 static_rate[0x4];
9002 u8 sl_eth_prio[0x4];
9003 u8 fl[0x1];
9004 u8 mlid[0x7];
9005 u8 rlid_udp_sport[0x10];
9007 u8 reserved_at_80[0x20];
9009 u8 rmac_47_16[0x20];
9011 u8 rmac_15_0[0x10];
9012 u8 tclass[0x8];
9013 u8 hop_limit[0x8];
9015 u8 reserved_at_e0[0x1];
9016 u8 grh[0x1];
9017 u8 reserved_at_e2[0x2];
9018 u8 src_addr_index[0x8];
9019 u8 flow_label[0x14];
9021 u8 rgid_rip[16][0x8];
9025 u8 reserved_at_0[0x10];
9026 u8 function_id[0x10];
9028 u8 num_pages[0x20];
9030 u8 reserved_at_40[0xa0];
9034 u8 reserved_at_0[0x8];
9035 u8 event_type[0x8];
9036 u8 reserved_at_10[0x8];
9037 u8 event_sub_type[0x8];
9039 u8 reserved_at_20[0xe0];
9043 u8 reserved_at_1e0[0x10];
9044 u8 signature[0x8];
9045 u8 reserved_at_1f8[0x7];
9046 u8 owner[0x1];
9050 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
9054 u8 type[0x8];
9055 u8 reserved_at_8[0x18];
9057 u8 input_length[0x20];
9059 u8 input_mailbox_pointer_63_32[0x20];
9061 u8 input_mailbox_pointer_31_9[0x17];
9062 u8 reserved_at_77[0x9];
9064 u8 command_input_inline_data[16][0x8];
9066 u8 command_output_inline_data[16][0x8];
9068 u8 output_mailbox_pointer_63_32[0x20];
9070 u8 output_mailbox_pointer_31_9[0x17];
9071 u8 reserved_at_1b7[0x9];
9073 u8 output_length[0x20];
9075 u8 token[0x8];
9076 u8 signature[0x8];
9077 u8 reserved_at_1f0[0x8];
9078 u8 status[0x7];
9079 u8 ownership[0x1];
9083 u8 status[0x8];
9084 u8 reserved_at_8[0x18];
9086 u8 syndrome[0x20];
9088 u8 command_output[0x20];
9092 u8 opcode[0x10];
9093 u8 reserved_at_10[0x10];
9095 u8 reserved_at_20[0x10];
9096 u8 op_mod[0x10];
9098 u8 command[0][0x20];
9102 u8 mailbox_data[512][0x8];
9104 u8 reserved_at_1000[0x180];
9106 u8 next_pointer_63_32[0x20];
9108 u8 next_pointer_31_10[0x16];
9109 u8 reserved_at_11b6[0xa];
9111 u8 block_number[0x20];
9113 u8 reserved_at_11e0[0x8];
9114 u8 token[0x8];
9115 u8 ctrl_signature[0x8];
9116 u8 signature[0x8];
9120 u8 ptag_63_32[0x20];
9122 u8 ptag_31_8[0x18];
9123 u8 reserved_at_38[0x6];
9124 u8 wr_en[0x1];
9125 u8 rd_en[0x1];
9129 u8 status[0x8];
9130 u8 reserved_at_8[0x18];
9132 u8 syndrome[0x20];
9134 u8 reserved_at_40[0x10];
9135 u8 rol_mode[0x8];
9136 u8 wol_mode[0x8];
9138 u8 reserved_at_60[0x20];
9142 u8 opcode[0x10];
9143 u8 reserved_at_10[0x10];
9145 u8 reserved_at_20[0x10];
9146 u8 op_mod[0x10];
9148 u8 reserved_at_40[0x40];
9152 u8 status[0x8];
9153 u8 reserved_at_8[0x18];
9155 u8 syndrome[0x20];
9157 u8 reserved_at_40[0x40];
9161 u8 opcode[0x10];
9162 u8 reserved_at_10[0x10];
9164 u8 reserved_at_20[0x10];
9165 u8 op_mod[0x10];
9167 u8 rol_mode_valid[0x1];
9168 u8 wol_mode_valid[0x1];
9169 u8 reserved_at_42[0xe];
9170 u8 rol_mode[0x8];
9171 u8 wol_mode[0x8];
9173 u8 reserved_at_60[0x20];
9177 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
9178 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
9179 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
9183 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
9184 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
9185 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
9189 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
9190 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
9191 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
9192 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
9193 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
9194 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
9195 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
9196 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
9197 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
9198 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
9199 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
9203 u8 fw_rev_minor[0x10];
9204 u8 fw_rev_major[0x10];
9206 u8 cmd_interface_rev[0x10];
9207 u8 fw_rev_subminor[0x10];
9209 u8 reserved_at_40[0x40];
9211 u8 cmdq_phy_addr_63_32[0x20];
9213 u8 cmdq_phy_addr_31_12[0x14];
9214 u8 reserved_at_b4[0x2];
9215 u8 nic_interface[0x2];
9216 u8 log_cmdq_size[0x4];
9217 u8 log_cmdq_stride[0x4];
9219 u8 command_doorbell_vector[0x20];
9221 u8 reserved_at_e0[0xf00];
9223 u8 initializing[0x1];
9224 u8 reserved_at_fe1[0x4];
9225 u8 nic_interface_supported[0x3];
9226 u8 embedded_cpu[0x1];
9227 u8 reserved_at_fe9[0x17];
9231 u8 no_dram_nic_offset[0x20];
9233 u8 reserved_at_1220[0x6e40];
9235 u8 reserved_at_8060[0x1f];
9236 u8 clear_int[0x1];
9238 u8 health_syndrome[0x8];
9239 u8 health_counter[0x18];
9241 u8 reserved_at_80a0[0x17fc0];
9245 u8 reserved_at_0[0xc];
9246 u8 cap_number_of_pps_pins[0x4];
9247 u8 reserved_at_10[0x4];
9248 u8 cap_max_num_of_pps_in_pins[0x4];
9249 u8 reserved_at_18[0x4];
9250 u8 cap_max_num_of_pps_out_pins[0x4];
9252 u8 reserved_at_20[0x24];
9253 u8 cap_pin_3_mode[0x4];
9254 u8 reserved_at_48[0x4];
9255 u8 cap_pin_2_mode[0x4];
9256 u8 reserved_at_50[0x4];
9257 u8 cap_pin_1_mode[0x4];
9258 u8 reserved_at_58[0x4];
9259 u8 cap_pin_0_mode[0x4];
9261 u8 reserved_at_60[0x4];
9262 u8 cap_pin_7_mode[0x4];
9263 u8 reserved_at_68[0x4];
9264 u8 cap_pin_6_mode[0x4];
9265 u8 reserved_at_70[0x4];
9266 u8 cap_pin_5_mode[0x4];
9267 u8 reserved_at_78[0x4];
9268 u8 cap_pin_4_mode[0x4];
9270 u8 field_select[0x20];
9271 u8 reserved_at_a0[0x60];
9273 u8 enable[0x1];
9274 u8 reserved_at_101[0xb];
9275 u8 pattern[0x4];
9276 u8 reserved_at_110[0x4];
9277 u8 pin_mode[0x4];
9278 u8 pin[0x8];
9280 u8 reserved_at_120[0x20];
9282 u8 time_stamp[0x40];
9284 u8 out_pulse_duration[0x10];
9285 u8 out_periodic_adjustment[0x10];
9286 u8 enhanced_out_periodic_adjustment[0x20];
9288 u8 reserved_at_1c0[0x20];
9292 u8 reserved_at_0[0x18];
9293 u8 pin[0x8];
9294 u8 event_arm[0x1];
9295 u8 reserved_at_21[0x1b];
9296 u8 event_generation_mode[0x4];
9297 u8 reserved_at_40[0x40];
9301 u8 last_index_flag[0x1];
9302 u8 reserved_at_1[0x7];
9303 u8 fw_device[0x8];
9304 u8 component_index[0x10];
9306 u8 reserved_at_20[0x10];
9307 u8 identifier[0x10];
9309 u8 reserved_at_40[0x17];
9310 u8 component_status[0x5];
9311 u8 component_update_state[0x4];
9313 u8 last_update_state_changer_type[0x4];
9314 u8 last_update_state_changer_host_id[0x4];
9315 u8 reserved_at_68[0x18];
9319 u8 supported_info_bitmask[0x20];
9321 u8 component_size[0x20];
9323 u8 max_component_size[0x20];
9325 u8 log_mcda_word_size[0x4];
9326 u8 reserved_at_64[0xc];
9327 u8 mcda_max_write_size[0x10];
9329 u8 rd_en[0x1];
9330 u8 reserved_at_81[0x1];
9331 u8 match_chip_id[0x1];
9332 u8 match_psid[0x1];
9333 u8 check_user_timestamp[0x1];
9334 u8 match_base_guid_mac[0x1];
9335 u8 reserved_at_86[0x1a];
9339 u8 reserved_at_0[0x2];
9340 u8 build_time_valid[0x1];
9341 u8 user_defined_time_valid[0x1];
9342 u8 reserved_at_4[0x14];
9343 u8 version_string_length[0x8];
9345 u8 version[0x20];
9347 u8 build_time[0x40];
9349 u8 user_defined_time[0x40];
9351 u8 build_tool_version[0x20];
9353 u8 reserved_at_e0[0x20];
9355 u8 version_string[92][0x8];
9359 u8 pending_server_ac_power_cycle[0x1];
9360 u8 pending_server_dc_power_cycle[0x1];
9361 u8 pending_server_reboot[0x1];
9362 u8 pending_fw_reset[0x1];
9363 u8 auto_activate[0x1];
9364 u8 all_hosts_sync[0x1];
9365 u8 device_hw_reset[0x1];
9366 u8 reserved_at_7[0x19];
9376 u8 read_pending_component[0x1];
9377 u8 reserved_at_1[0xf];
9378 u8 component_index[0x10];
9380 u8 reserved_at_20[0x20];
9382 u8 reserved_at_40[0x1b];
9383 u8 info_type[0x5];
9385 u8 info_size[0x20];
9387 u8 offset[0x20];
9389 u8 reserved_at_a0[0x10];
9390 u8 data_size[0x10];
9392 union mlx5_ifc_mcqi_reg_data_bits data[0];
9396 u8 reserved_at_0[0x4];
9397 u8 time_elapsed_since_last_cmd[0xc];
9398 u8 reserved_at_10[0x8];
9399 u8 instruction[0x8];
9401 u8 reserved_at_20[0x10];
9402 u8 component_index[0x10];
9404 u8 reserved_at_40[0x8];
9405 u8 update_handle[0x18];
9407 u8 handle_owner_type[0x4];
9408 u8 handle_owner_host_id[0x4];
9409 u8 reserved_at_68[0x1];
9410 u8 control_progress[0x7];
9411 u8 error_code[0x8];
9412 u8 reserved_at_78[0x4];
9413 u8 control_state[0x4];
9415 u8 component_size[0x20];
9417 u8 reserved_at_a0[0x60];
9421 u8 reserved_at_0[0x8];
9422 u8 update_handle[0x18];
9424 u8 offset[0x20];
9426 u8 reserved_at_40[0x10];
9427 u8 size[0x10];
9429 u8 reserved_at_60[0x20];
9431 u8 data[0][0x20];
9489 u8 reserved_at_0[0x60e0];
9494 u8 reserved_at_0[0x200];
9499 u8 reserved_at_0[0x20060];
9503 u8 status[0x8];
9504 u8 reserved_at_8[0x18];
9506 u8 syndrome[0x20];
9508 u8 reserved_at_40[0x40];
9512 u8 opcode[0x10];
9513 u8 reserved_at_10[0x10];
9515 u8 reserved_at_20[0x10];
9516 u8 op_mod[0x10];
9518 u8 other_vport[0x1];
9519 u8 reserved_at_41[0xf];
9520 u8 vport_number[0x10];
9522 u8 reserved_at_60[0x20];
9524 u8 table_type[0x8];
9525 u8 reserved_at_88[0x18];
9527 u8 reserved_at_a0[0x8];
9528 u8 table_id[0x18];
9530 u8 reserved_at_c0[0x8];
9531 u8 underlay_qpn[0x18];
9532 u8 reserved_at_e0[0x120];
9536 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
9541 u8 status[0x8];
9542 u8 reserved_at_8[0x18];
9544 u8 syndrome[0x20];
9546 u8 reserved_at_40[0x40];
9550 u8 opcode[0x10];
9551 u8 reserved_at_10[0x10];
9553 u8 reserved_at_20[0x10];
9554 u8 op_mod[0x10];
9556 u8 other_vport[0x1];
9557 u8 reserved_at_41[0xf];
9558 u8 vport_number[0x10];
9560 u8 reserved_at_60[0x10];
9561 u8 modify_field_select[0x10];
9563 u8 table_type[0x8];
9564 u8 reserved_at_88[0x18];
9566 u8 reserved_at_a0[0x8];
9567 u8 table_id[0x18];
9573 u8 g[0x1];
9574 u8 b[0x1];
9575 u8 r[0x1];
9576 u8 reserved_at_3[0x9];
9577 u8 group[0x4];
9578 u8 reserved_at_10[0x9];
9579 u8 bw_allocation[0x7];
9581 u8 reserved_at_20[0xc];
9582 u8 max_bw_units[0x4];
9583 u8 reserved_at_30[0x8];
9584 u8 max_bw_value[0x8];
9588 u8 reserved_at_0[0x2];
9589 u8 r[0x1];
9590 u8 reserved_at_3[0x1d];
9592 u8 reserved_at_20[0xc];
9593 u8 max_bw_units[0x4];
9594 u8 reserved_at_30[0x8];
9595 u8 max_bw_value[0x8];
9599 u8 reserved_at_0[0x8];
9600 u8 port_number[0x8];
9601 u8 reserved_at_10[0x30];
9603 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
9608 u8 e[0x1];
9609 u8 reserved_at_01[0x0b];
9610 u8 prio[0x04];
9614 u8 reserved_at_0[0x8];
9615 u8 local_port[0x8];
9616 u8 reserved_at_10[0x10];
9621 u8 reserved_at_0[0x8];
9622 u8 local_port[0x8];
9623 u8 reserved_at_10[0x2d];
9624 u8 trust_state[0x3];
9628 u8 reserved_at_0[0x2];
9629 u8 mm[0x2];
9630 u8 reserved_at_4[0x4];
9631 u8 local_port[0x8];
9632 u8 reserved_at_10[0x6];
9633 u8 cm[0x1];
9634 u8 um[0x1];
9635 u8 pm[0x8];
9637 u8 prio_x_buff[0x20];
9639 u8 pm_msb[0x8];
9640 u8 reserved_at_48[0x10];
9641 u8 ctrl_buff[0x4];
9642 u8 untagged_buff[0x4];
9646 u8 reserved_at_0[0x8];
9647 u8 local_port[0x8];
9648 u8 reserved_at_10[0x10];
9650 u8 xoff_timer_value[0x10];
9651 u8 xoff_refresh[0x10];
9653 u8 reserved_at_40[0x9];
9654 u8 fullness_threshold[0x7];
9655 u8 port_buffer_size[0x10];
9659 u8 reserved_at_2e0[0x40];
9663 u8 reserved_at_0[0x8];
9664 u8 port_number[0x8];
9665 u8 reserved_at_10[0xd];
9666 u8 prio[0x3];
9668 u8 reserved_at_20[0x1d];
9669 u8 tclass[0x3];
9673 u8 l[0x1];
9674 u8 reserved_at_1[0x7];
9675 u8 module[0x8];
9676 u8 reserved_at_10[0x8];
9677 u8 status[0x8];
9679 u8 i2c_device_address[0x8];
9680 u8 page_number[0x8];
9681 u8 device_address[0x10];
9683 u8 reserved_at_40[0x10];
9684 u8 size[0x10];
9686 u8 reserved_at_60[0x20];
9688 u8 dword_0[0x20];
9689 u8 dword_1[0x20];
9690 u8 dword_2[0x20];
9691 u8 dword_3[0x20];
9692 u8 dword_4[0x20];
9693 u8 dword_5[0x20];
9694 u8 dword_6[0x20];
9695 u8 dword_7[0x20];
9696 u8 dword_8[0x20];
9697 u8 dword_9[0x20];
9698 u8 dword_10[0x20];
9699 u8 dword_11[0x20];
9703 u8 dcbx_cee_cap[0x1];
9704 u8 dcbx_ieee_cap[0x1];
9705 u8 dcbx_standby_cap[0x1];
9706 u8 reserved_at_3[0x5];
9707 u8 port_number[0x8];
9708 u8 reserved_at_10[0xa];
9710 u8 reserved_at_20[0x15];
9711 u8 version_oper[0x3];
9713 u8 version_admin[0x3];
9714 u8 willing_admin[0x1];
9715 u8 reserved_at_41[0x3];
9716 u8 pfc_cap_oper[0x4];
9717 u8 reserved_at_48[0x4];
9718 u8 pfc_cap_admin[0x4];
9719 u8 reserved_at_50[0x4];
9720 u8 num_of_tc_oper[0x4];
9721 u8 reserved_at_58[0x4];
9722 u8 num_of_tc_admin[0x4];
9723 u8 remote_willing[0x1];
9726 u8 reserved_at_68[0x14];
9727 u8 remote_num_of_tc[0x4];
9728 u8 reserved_at_80[0x18];
9729 u8 error[0x8];
9730 u8 reserved_at_a0[0x160];
9734 u8 reserved_at_0[0x1d];
9735 u8 lag_state[0x3];
9737 u8 reserved_at_20[0x14];
9738 u8 tx_remap_affinity_2[0x4];
9739 u8 reserved_at_38[0x4];
9740 u8 tx_remap_affinity_1[0x4];
9744 u8 status[0x8];
9745 u8 reserved_at_8[0x18];
9747 u8 syndrome[0x20];
9749 u8 reserved_at_40[0x40];
9753 u8 opcode[0x10];
9754 u8 reserved_at_10[0x10];
9756 u8 reserved_at_20[0x10];
9757 u8 op_mod[0x10];
9763 u8 status[0x8];
9764 u8 reserved_at_8[0x18];
9766 u8 syndrome[0x20];
9768 u8 reserved_at_40[0x40];
9772 u8 opcode[0x10];
9773 u8 reserved_at_10[0x10];
9775 u8 reserved_at_20[0x10];
9776 u8 op_mod[0x10];
9778 u8 reserved_at_40[0x20];
9779 u8 field_select[0x20];
9785 u8 status[0x8];
9786 u8 reserved_at_8[0x18];
9788 u8 syndrome[0x20];
9794 u8 opcode[0x10];
9795 u8 reserved_at_10[0x10];
9797 u8 reserved_at_20[0x10];
9798 u8 op_mod[0x10];
9800 u8 reserved_at_40[0x40];
9804 u8 status[0x8];
9805 u8 reserved_at_8[0x18];
9807 u8 syndrome[0x20];
9809 u8 reserved_at_40[0x40];
9813 u8 opcode[0x10];
9814 u8 reserved_at_10[0x10];
9816 u8 reserved_at_20[0x10];
9817 u8 op_mod[0x10];
9819 u8 reserved_at_40[0x40];
9823 u8 status[0x8];
9824 u8 reserved_at_8[0x18];
9826 u8 syndrome[0x20];
9828 u8 reserved_at_40[0x40];
9832 u8 opcode[0x10];
9833 u8 reserved_at_10[0x10];
9835 u8 reserved_at_20[0x10];
9836 u8 op_mod[0x10];
9838 u8 reserved_at_40[0x40];
9842 u8 status[0x8];
9843 u8 reserved_at_8[0x18];
9845 u8 syndrome[0x20];
9847 u8 reserved_at_40[0x40];
9851 u8 opcode[0x10];
9852 u8 reserved_at_10[0x10];
9854 u8 reserved_at_20[0x10];
9855 u8 op_mod[0x10];
9857 u8 reserved_at_40[0x40];
9861 u8 opcode[0x10];
9862 u8 reserved_at_10[0x10];
9864 u8 reserved_at_20[0x10];
9865 u8 op_mod[0x10];
9867 u8 reserved_at_30[0x20];
9869 u8 reserved_at_40[0x18];
9870 u8 log_memic_addr_alignment[0x8];
9872 u8 range_start_addr[0x40];
9874 u8 range_size[0x20];
9876 u8 memic_size[0x20];
9880 u8 status[0x8];
9881 u8 reserved_at_8[0x18];
9883 u8 syndrome[0x20];
9885 u8 memic_start_addr[0x40];
9889 u8 opcode[0x10];
9890 u8 reserved_at_10[0x10];
9892 u8 reserved_at_20[0x10];
9893 u8 op_mod[0x10];
9895 u8 reserved_at_40[0x40];
9897 u8 memic_start_addr[0x40];
9899 u8 memic_size[0x20];
9901 u8 reserved_at_e0[0x20];
9905 u8 status[0x8];
9906 u8 reserved_at_8[0x18];
9908 u8 syndrome[0x20];
9910 u8 reserved_at_40[0x40];
9914 u8 opcode[0x10];
9915 u8 uid[0x10];
9917 u8 vhca_tunnel_id[0x10];
9918 u8 obj_type[0x10];
9920 u8 obj_id[0x20];
9922 u8 reserved_at_60[0x20];
9926 u8 status[0x8];
9927 u8 reserved_at_8[0x18];
9929 u8 syndrome[0x20];
9931 u8 obj_id[0x20];
9933 u8 reserved_at_60[0x20];
9937 u8 reserved_at_0[0x80];
9939 u8 reserved_at_80[0x1b];
9940 u8 log_page_size[0x5];
9942 u8 page_offset[0x20];
9944 u8 num_of_mtt[0x40];
9946 struct mlx5_ifc_mtt_bits mtt[0];
9950 u8 cap[0x20];
9952 u8 reserved_at_20[0x160];
9956 u8 modify_field_select[0x40];
9958 u8 reserved_at_40[0x18];
9959 u8 log_sw_icm_size[0x8];
9961 u8 reserved_at_60[0x20];
9963 u8 sw_icm_start_addr[0x40];
9965 u8 reserved_at_c0[0x140];
9969 u8 modify_field_select[0x40];
9971 u8 reserved_at_40[0x18];
9972 u8 geneve_option_fte_index[0x8];
9974 u8 option_class[0x10];
9975 u8 option_type[0x8];
9976 u8 reserved_at_78[0x3];
9977 u8 option_data_length[0x5];
9979 u8 reserved_at_80[0x180];
9983 u8 opcode[0x10];
9984 u8 uid[0x10];
9986 u8 reserved_at_20[0x10];
9987 u8 op_mod[0x10];
9989 u8 reserved_at_40[0x40];
9995 u8 opcode[0x10];
9996 u8 reserved_at_10[0x10];
9998 u8 reserved_at_20[0x10];
9999 u8 op_mod[0x10];
10001 u8 reserved_at_40[0x40];
10007 u8 opcode[0x10];
10008 u8 reserved_at_10[0x10];
10010 u8 reserved_at_20[0x10];
10011 u8 op_mod[0x10];
10013 u8 reserved_at_40[0x10];
10014 u8 uid[0x10];
10016 u8 reserved_at_60[0x20];
10030 u8 string_db_base_address[0x20];
10032 u8 reserved_at_20[0x8];
10033 u8 string_db_size[0x18];
10037 u8 trace_owner[0x1];
10038 u8 trace_to_memory[0x1];
10039 u8 reserved_at_2[0x4];
10040 u8 trc_ver[0x2];
10041 u8 reserved_at_8[0x14];
10042 u8 num_string_db[0x4];
10044 u8 first_string_trace[0x8];
10045 u8 num_string_trace[0x8];
10046 u8 reserved_at_30[0x28];
10048 u8 log_max_trace_buffer_size[0x8];
10050 u8 reserved_at_60[0x20];
10054 u8 reserved_at_280[0x180];
10058 u8 reserved_at_0[0x1c];
10059 u8 trace_mode[0x4];
10060 u8 reserved_at_20[0x18];
10061 u8 log_trace_buffer_size[0x8];
10062 u8 trace_mkey[0x20];
10063 u8 reserved_at_60[0x3a0];
10067 u8 string_db_index[0x4];
10068 u8 reserved_at_4[0x4];
10069 u8 read_size[0x18];
10070 u8 start_offset[0x20];
10071 u8 string_db_data[0];
10075 u8 trace_status[0x2];
10076 u8 reserved_at_2[0x2];
10077 u8 arm_event[0x1];
10078 u8 reserved_at_5[0xb];
10079 u8 modify_field_select[0x10];
10080 u8 reserved_at_20[0x2b];
10081 u8 current_timestamp52_32[0x15];
10082 u8 current_timestamp31_0[0x20];
10083 u8 reserved_at_80[0x180];
10087 u8 host_number[0x8];
10088 u8 reserved_at_8[0x7];
10089 u8 host_pf_disabled[0x1];
10090 u8 host_num_of_vfs[0x10];
10092 u8 host_total_vfs[0x10];
10093 u8 host_pci_bus[0x10];
10095 u8 reserved_at_40[0x10];
10096 u8 host_pci_device[0x10];
10098 u8 reserved_at_60[0x10];
10099 u8 host_pci_function[0x10];
10101 u8 reserved_at_80[0x180];
10105 u8 opcode[0x10];
10106 u8 reserved_at_10[0x10];
10108 u8 reserved_at_20[0x10];
10109 u8 op_mod[0x10];
10111 u8 reserved_at_40[0x40];
10115 u8 status[0x8];
10116 u8 reserved_at_8[0x18];
10118 u8 syndrome[0x20];
10120 u8 reserved_at_40[0x40];
10124 u8 reserved_at_280[0x180];
10125 u8 host_sf_enable[0][0x40];
10129 u8 reserved_at_0[0x10];
10130 u8 log_num_sf[0x8];
10131 u8 log_sf_bar_size[0x8];
10135 u8 status[0x8];
10136 u8 reserved_at_8[0x18];
10138 u8 syndrome[0x20];
10140 u8 reserved_at_40[0x18];
10141 u8 num_sf_partitions[0x8];
10143 u8 reserved_at_60[0x20];
10145 struct mlx5_ifc_sf_partition_bits sf_partition[0];
10149 u8 opcode[0x10];
10150 u8 reserved_at_10[0x10];
10152 u8 reserved_at_20[0x10];
10153 u8 op_mod[0x10];
10155 u8 reserved_at_40[0x40];
10159 u8 status[0x8];
10160 u8 reserved_at_8[0x18];
10162 u8 syndrome[0x20];
10164 u8 reserved_at_40[0x40];
10168 u8 opcode[0x10];
10169 u8 reserved_at_10[0x10];
10171 u8 reserved_at_20[0x10];
10172 u8 op_mod[0x10];
10174 u8 reserved_at_40[0x10];
10175 u8 function_id[0x10];
10177 u8 reserved_at_60[0x20];
10181 u8 status[0x8];
10182 u8 reserved_at_8[0x18];
10184 u8 syndrome[0x20];
10186 u8 reserved_at_40[0x40];
10190 u8 opcode[0x10];
10191 u8 reserved_at_10[0x10];
10193 u8 reserved_at_20[0x10];
10194 u8 op_mod[0x10];
10196 u8 reserved_at_40[0x10];
10197 u8 function_id[0x10];
10199 u8 reserved_at_60[0x20];
10203 u8 reserved_at_0[0x10];
10204 u8 obj_type[0x10];
10206 u8 obj_id[0x20];
10210 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
10214 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
10218 u8 modify_field_select[0x40];
10220 u8 reserved_at_40[0x14];
10221 u8 key_size[0x4];
10222 u8 reserved_at_58[0x4];
10223 u8 key_type[0x4];
10225 u8 reserved_at_60[0x8];
10226 u8 pd[0x18];
10228 u8 reserved_at_80[0x180];
10229 u8 key[8][0x20];
10231 u8 reserved_at_300[0x500];
10240 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10241 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10245 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1,
10249 u8 const_2[0x2];
10250 u8 tls_version[0x4];
10251 u8 const_1[0x2];
10252 u8 reserved_at_8[0x14];
10253 u8 encryption_standard[0x4];
10255 u8 reserved_at_20[0x20];
10257 u8 initial_record_number[0x40];
10259 u8 resync_tcp_sn[0x20];
10261 u8 gcm_iv[0x20];
10263 u8 implicit_iv[0x40];
10265 u8 reserved_at_100[0x8];
10266 u8 dek_index[0x18];
10268 u8 reserved_at_120[0xe0];
10272 u8 reserved_at_0[0x8];
10273 u8 tisn[0x18];
10275 u8 next_record_tcp_sn[0x20];
10277 u8 hw_resync_tcp_sn[0x20];
10279 u8 record_tracker_state[0x2];
10280 u8 auth_state[0x2];
10281 u8 reserved_at_64[0x4];
10282 u8 hw_offset_record_number[0x18];