1138 #define MLX5_CAP_GEN(mdev, cap) \  argument
1139 	MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
1141 #define MLX5_CAP_GEN_64(mdev, cap) \  argument
1142 	MLX5_GET64(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
1144 #define MLX5_CAP_GEN_MAX(mdev, cap) \  argument
1145 	MLX5_GET(cmd_hca_cap, mdev->caps.hca_max[MLX5_CAP_GENERAL], cap)
1147 #define MLX5_CAP_ETH(mdev, cap) \  argument
1149 		 mdev->caps.hca_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1151 #define MLX5_CAP_ETH_MAX(mdev, cap) \  argument
1153 		 mdev->caps.hca_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1155 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \  argument
1157 		 mdev->caps.hca_cur[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS], cap)
1159 #define MLX5_CAP_ROCE(mdev, cap) \  argument
1160 	MLX5_GET(roce_cap, mdev->caps.hca_cur[MLX5_CAP_ROCE], cap)
1162 #define MLX5_CAP_ROCE_MAX(mdev, cap) \  argument
1163 	MLX5_GET(roce_cap, mdev->caps.hca_max[MLX5_CAP_ROCE], cap)
1165 #define MLX5_CAP_ATOMIC(mdev, cap) \  argument
1166 	MLX5_GET(atomic_caps, mdev->caps.hca_cur[MLX5_CAP_ATOMIC], cap)
1168 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \  argument
1169 	MLX5_GET(atomic_caps, mdev->caps.hca_max[MLX5_CAP_ATOMIC], cap)
1171 #define MLX5_CAP_FLOWTABLE(mdev, cap) \  argument
1172 	MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
1174 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \  argument
1175 	MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
1177 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \  argument
1178 	MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap)
1180 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \  argument
1181 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1183 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \  argument
1184 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1186 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \  argument
1187 		MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap)
1189 #define MLX5_CAP_FLOWTABLE_NIC_TX_MAX(mdev, cap) \  argument
1190 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit.cap)
1192 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \  argument
1193 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1195 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \  argument
1196 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
1198 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \  argument
1199 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1201 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \  argument
1202 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1204 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \  argument
1205 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap)
1207 #define MLX5_CAP_FLOWTABLE_RDMA_RX_MAX(mdev, cap) \  argument
1208 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_rdma.cap)
1210 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \  argument
1212 		 mdev->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1214 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \  argument
1216 		 mdev->caps.hca_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1218 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \  argument
1219 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1221 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \  argument
1222 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1224 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \  argument
1225 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1227 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \  argument
1228 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1230 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \  argument
1231 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1233 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \  argument
1234 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1236 #define MLX5_CAP_ESW(mdev, cap) \  argument
1238 		 mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap)
1240 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \  argument
1242 		(mdev)->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1244 #define MLX5_CAP_ESW_MAX(mdev, cap) \  argument
1246 		 mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap)
1248 #define MLX5_CAP_ODP(mdev, cap)\  argument
1249 	MLX5_GET(odp_cap, mdev->caps.hca_cur[MLX5_CAP_ODP], cap)
1251 #define MLX5_CAP_ODP_MAX(mdev, cap)\  argument
1252 	MLX5_GET(odp_cap, mdev->caps.hca_max[MLX5_CAP_ODP], cap)
1254 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \  argument
1256 		 mdev->caps.hca_cur[MLX5_CAP_VECTOR_CALC], cap)
1258 #define MLX5_CAP_QOS(mdev, cap)\  argument
1259 	MLX5_GET(qos_cap, mdev->caps.hca_cur[MLX5_CAP_QOS], cap)
1261 #define MLX5_CAP_DEBUG(mdev, cap)\  argument
1262 	MLX5_GET(debug_cap, mdev->caps.hca_cur[MLX5_CAP_DEBUG], cap)
1282 #define MLX5_CAP_FPGA(mdev, cap) \  argument
1283 	MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1285 #define MLX5_CAP64_FPGA(mdev, cap) \  argument
1286 	MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1288 #define MLX5_CAP_DEV_MEM(mdev, cap)\  argument
1289 	MLX5_GET(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
1291 #define MLX5_CAP64_DEV_MEM(mdev, cap)\  argument
1292 	MLX5_GET64(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
1294 #define MLX5_CAP_TLS(mdev, cap) \  argument
1295 	MLX5_GET(tls_cap, (mdev)->caps.hca_cur[MLX5_CAP_TLS], cap)
1297 #define MLX5_CAP_DEV_EVENT(mdev, cap)\  argument
1298 	MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca_cur[MLX5_CAP_DEV_EVENT], cap)