Lines Matching refs:BIT
96 #define LP87565_BUCK_CTRL_1_EN BIT(7)
97 #define LP87565_BUCK_CTRL_1_EN_PIN_CTRL BIT(6)
100 #define LP87565_BUCK_CTRL_1_ROOF_FLOOR_EN BIT(3)
101 #define LP87565_BUCK_CTRL_1_RDIS_EN BIT(2)
102 #define LP87565_BUCK_CTRL_1_FPWM BIT(1)
104 #define LP87565_BUCK_CTRL_1_FPWM_MP_0_2 BIT(0)
118 #define LP87565_RESET_SW_RESET BIT(0)
120 #define LP87565_CONFIG_DOUBLE_DELAY BIT(7)
121 #define LP87565_CONFIG_CLKIN_PD BIT(6)
122 #define LP87565_CONFIG_EN4_PD BIT(5)
123 #define LP87565_CONFIG_EN3_PD BIT(4)
124 #define LP87565_CONFIG_TDIE_WARN_LEVEL BIT(3)
125 #define LP87565_CONFIG_EN2_PD BIT(2)
126 #define LP87565_CONFIG_EN1_PD BIT(1)
128 #define LP87565_INT_GPIO BIT(7)
129 #define LP87565_INT_BUCK23 BIT(6)
130 #define LP87565_INT_BUCK01 BIT(5)
131 #define LP87565_NO_SYNC_CLK BIT(4)
132 #define LP87565_TDIE_SD BIT(3)
133 #define LP87565_TDIE_WARN BIT(2)
134 #define LP87565_INT_OVP BIT(1)
135 #define LP87565_I_LOAD_READY BIT(0)
137 #define LP87565_INT_TOP2_RESET_REG BIT(0)
139 #define LP87565_BUCK1_PG_INT BIT(6)
140 #define LP87565_BUCK1_SC_INT BIT(5)
141 #define LP87565_BUCK1_ILIM_INT BIT(4)
142 #define LP87565_BUCK0_PG_INT BIT(2)
143 #define LP87565_BUCK0_SC_INT BIT(1)
144 #define LP87565_BUCK0_ILIM_INT BIT(0)
146 #define LP87565_BUCK3_PG_INT BIT(6)
147 #define LP87565_BUCK3_SC_INT BIT(5)
148 #define LP87565_BUCK3_ILIM_INT BIT(4)
149 #define LP87565_BUCK2_PG_INT BIT(2)
150 #define LP87565_BUCK2_SC_INT BIT(1)
151 #define LP87565_BUCK2_ILIM_INT BIT(0)
153 #define LP87565_SYNC_CLK_STAT BIT(4)
154 #define LP87565_TDIE_SD_STAT BIT(3)
155 #define LP87565_TDIE_WARN_STAT BIT(2)
156 #define LP87565_OVP_STAT BIT(1)
158 #define LP87565_BUCK1_STAT BIT(7)
159 #define LP87565_BUCK1_PG_STAT BIT(6)
160 #define LP87565_BUCK1_ILIM_STAT BIT(4)
161 #define LP87565_BUCK0_STAT BIT(3)
162 #define LP87565_BUCK0_PG_STAT BIT(2)
163 #define LP87565_BUCK0_ILIM_STAT BIT(0)
165 #define LP87565_BUCK3_STAT BIT(7)
166 #define LP87565_BUCK3_PG_STAT BIT(6)
167 #define LP87565_BUCK3_ILIM_STAT BIT(4)
168 #define LP87565_BUCK2_STAT BIT(3)
169 #define LP87565_BUCK2_PG_STAT BIT(2)
170 #define LP87565_BUCK2_ILIM_STAT BIT(0)
172 #define LPL87565_GPIO_MASK BIT(7)
173 #define LPL87565_SYNC_CLK_MASK BIT(4)
174 #define LPL87565_TDIE_WARN_MASK BIT(2)
175 #define LPL87565_I_LOAD_READY_MASK BIT(0)
177 #define LPL87565_RESET_REG_MASK BIT(0)
179 #define LPL87565_BUCK1_PG_MASK BIT(6)
180 #define LPL87565_BUCK1_ILIM_MASK BIT(4)
181 #define LPL87565_BUCK0_PG_MASK BIT(2)
182 #define LPL87565_BUCK0_ILIM_MASK BIT(0)
184 #define LPL87565_BUCK3_PG_MASK BIT(6)
185 #define LPL87565_BUCK3_ILIM_MASK BIT(4)
186 #define LPL87565_BUCK2_PG_MASK BIT(2)
187 #define LPL87565_BUCK2_ILIM_MASK BIT(0)
199 #define LP87565_HALF_DAY BIT(7)
200 #define LP87565_EN_PG0_NINT BIT(6)
201 #define LP87565_PGOOD_SET_DELAY BIT(5)
202 #define LP87565_EN_PGFLT_STAT BIT(4)
203 #define LP87565_PGOOD_WINDOW BIT(2)
204 #define LP87565_PGOOD_OD BIT(1)
205 #define LP87565_PGOOD_POL BIT(0)
207 #define LP87565_PG3_FLT BIT(3)
208 #define LP87565_PG2_FLT BIT(2)
209 #define LP87565_PG1_FLT BIT(1)
210 #define LP87565_PG0_FLT BIT(0)
215 #define LP87565_EN_SPREAD_SPEC BIT(7)
216 #define LP87565_EN_PIN_CTRL_GPIO3 BIT(6)
217 #define LP87565_EN_PIN_SELECT_GPIO3 BIT(5)
218 #define LP87565_EN_PIN_CTRL_GPIO2 BIT(4)
219 #define LP87565_EN_PIN_SELECT_GPIO2 BIT(3)
220 #define LP87565_GPIO3_SEL BIT(2)
221 #define LP87565_GPIO2_SEL BIT(1)
222 #define LP87565_GPIO1_SEL BIT(0)
224 #define LP87565_GOIO3_OD BIT(6)
225 #define LP87565_GOIO2_OD BIT(5)
226 #define LP87565_GOIO1_OD BIT(4)
227 #define LP87565_GOIO3_DIR BIT(2)
228 #define LP87565_GOIO2_DIR BIT(1)
229 #define LP87565_GOIO1_DIR BIT(0)
231 #define LP87565_GOIO3_IN BIT(2)
232 #define LP87565_GOIO2_IN BIT(1)
233 #define LP87565_GOIO1_IN BIT(0)
235 #define LP87565_GOIO3_OUT BIT(2)
236 #define LP87565_GOIO2_OUT BIT(1)
237 #define LP87565_GOIO1_OUT BIT(0)