1 /* SPDX-License-Identifier: GPL-2.0 */
10  * Thanks. --rmk
36  * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
38  * IRQ_TYPE_NONE		- default, unspecified type
39  * IRQ_TYPE_EDGE_RISING		- rising edge triggered
40  * IRQ_TYPE_EDGE_FALLING	- falling edge triggered
41  * IRQ_TYPE_EDGE_BOTH		- rising and falling edge triggered
42  * IRQ_TYPE_LEVEL_HIGH		- high level triggered
43  * IRQ_TYPE_LEVEL_LOW		- low level triggered
44  * IRQ_TYPE_LEVEL_MASK		- Mask to filter out the level bits
45  * IRQ_TYPE_SENSE_MASK		- Mask for all the above bits
46  * IRQ_TYPE_DEFAULT		- For use by some PICs to ask irq_set_type
52  * IRQ_TYPE_PROBE		- Special flag for probing in progress
55  * IRQ_LEVEL			- Interrupt is level type. Will be also
58  * IRQ_PER_CPU			- Mark an interrupt PER_CPU. Will protect
59  *				  it from affinity setting
60  * IRQ_NOPROBE			- Interrupt cannot be probed by autoprobing
61  * IRQ_NOREQUEST		- Interrupt cannot be requested via
63  * IRQ_NOTHREAD			- Interrupt cannot be threaded
64  * IRQ_NOAUTOEN			- Interrupt is not automatically enabled in
66  * IRQ_NO_BALANCING		- Interrupt cannot be balanced (affinity set)
67  * IRQ_MOVE_PCNTXT		- Interrupt can be migrated from process context
68  * IRQ_NESTED_THREAD		- Interrupt nests into another thread
69  * IRQ_PER_CPU_DEVID		- Dev_id is a per-cpu variable
70  * IRQ_IS_POLLED		- Always polled by another interrupt. Exclude
71  *				  it from the spurious interrupt detection
73  * IRQ_DISABLE_UNLAZY		- Disable lazy irq disable
111  * Return value for chip->irq_set_affinity()
113  * IRQ_SET_MASK_OK	- OK, core updates irq_common_data.affinity
114  * IRQ_SET_MASK_NOCPY	- OK, chip did update irq_common_data.affinity
115  * IRQ_SET_MASK_OK_DONE	- Same as IRQ_SET_MASK_OK for core. Special code to
129  * struct irq_common_data - per irq data shared by all irqchips
133  * @handler_data:	per-IRQ data for the irq_chip methods
134  * @affinity:		IRQ affinity on SMP. If this is an IPI
137  * @effective_affinity:	The effective IRQ affinity on SMP as some irq
139  *			A subset of @affinity.
141  * @ipi_offset:		Offset of first IPI target cpu in @affinity. Optional.
150 	cpumask_var_t		affinity;  member
160  * struct irq_data - per irq chip data passed down to chip functions
162  * @irq:		interrupt number
163  * @hwirq:		hardware interrupt number, local to the interrupt domain
165  * @chip:		low level interrupt hardware access
166  * @domain:		Interrupt translation domain; responsible for mapping
170  * @chip_data:		platform-specific per-chip private data for the chip
189  * IRQD_TRIGGER_MASK		- Mask for the trigger type bits
190  * IRQD_SETAFFINITY_PENDING	- Affinity setting is pending
191  * IRQD_ACTIVATED		- Interrupt has already been activated
192  * IRQD_NO_BALANCING		- Balancing disabled for this IRQ
193  * IRQD_PER_CPU			- Interrupt is per cpu
194  * IRQD_AFFINITY_SET		- Interrupt affinity was set
195  * IRQD_LEVEL			- Interrupt is level triggered
196  * IRQD_WAKEUP_STATE		- Interrupt is configured for wakeup
198  * IRQD_MOVE_PCNTXT		- Interrupt can be moved in process
200  * IRQD_IRQ_DISABLED		- Disabled state of the interrupt
201  * IRQD_IRQ_MASKED		- Masked state of the interrupt
202  * IRQD_IRQ_INPROGRESS		- In progress state of the interrupt
203  * IRQD_WAKEUP_ARMED		- Wakeup mode armed
204  * IRQD_FORWARDED_TO_VCPU	- The interrupt is forwarded to a VCPU
205  * IRQD_AFFINITY_MANAGED	- Affinity is auto-managed by the kernel
206  * IRQD_IRQ_STARTED		- Startup state of the interrupt
207  * IRQD_MANAGED_SHUTDOWN	- Interrupt was shutdown due to empty affinity
208  *				  mask. Applies only to affinity managed irqs.
209  * IRQD_SINGLE_TARGET		- IRQ allows only a single affinity target
210  * IRQD_DEFAULT_TRIGGER_SET	- Expected trigger already been set
211  * IRQD_CAN_RESERVE		- Can use reservation mode
236 #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
397 	return d->hwirq;  in irqd_to_hwirq()
401  * struct irq_chip - hardware interrupt chip descriptor
405  * @irq_startup:	start up the interrupt (defaults to ->enable if NULL)
406  * @irq_shutdown:	shut down the interrupt (defaults to ->disable if NULL)
407  * @irq_enable:		enable the interrupt (defaults to chip->unmask if NULL)
408  * @irq_disable:	disable the interrupt
409  * @irq_ack:		start of a new interrupt
410  * @irq_mask:		mask an interrupt source
411  * @irq_mask_ack:	ack and mask an interrupt source
412  * @irq_unmask:		unmask an interrupt source
413  * @irq_eoi:		end of interrupt
414  * @irq_set_affinity:	Set the CPU affinity on SMP machines. If the force
416  *			unconditionally apply the affinity setting. Sanity
417  *			checks against the supplied affinity mask are not
422  * @irq_set_wake:	enable/disable power-management wake-on of an IRQ
425  * @irq_cpu_online:	configure an interrupt source for a secondary CPU
426  * @irq_cpu_offline:	un-configure an interrupt source for a secondary CPU
440  * @irq_get_irqchip_state:	return the internal state of an interrupt
441  * @irq_set_irqchip_state:	set the internal state of a interrupt
530  * Pick up the arch-dependent methods:
590  * Built-in IRQ handlers for various IRQ types,
591  * callable via desc->handle_irq()
639 /* Checks whether the interrupt can be requested by request_irq(): */
642 /* Dummy irq-chip implementations: */
658 					  const struct cpumask *affinity);
660 					  struct cpumask *affinity);
752 	return d ? d->chip : NULL;  in irq_get_chip()
757 	return d->chip;  in irq_data_get_irq_chip()
763 	return d ? d->chip_data : NULL;  in irq_get_chip_data()
768 	return d->chip_data;  in irq_data_get_irq_chip_data()
774 	return d ? d->common->handler_data : NULL;  in irq_get_handler_data()
779 	return d->common->handler_data;  in irq_data_get_irq_handler_data()
785 	return d ? d->common->msi_desc : NULL;  in irq_get_msi_desc()
790 	return d->common->msi_desc;  in irq_data_get_msi_desc()
802 	return d->node;  in irq_common_data_get_node()
810 	return irq_common_data_get_node(d->common);  in irq_data_get_node()
817 	return d ? d->common->affinity : NULL;  in irq_get_affinity_mask()
822 	return d->common->affinity;  in irq_data_get_affinity_mask()
829 	return d->common->effective_affinity;  in irq_data_get_effective_affinity_mask()
834 	cpumask_copy(d->common->effective_affinity, m);  in irq_data_update_effective_affinity()
844 	return d->common->affinity;  in irq_data_get_effective_affinity_mask()
852 		      const struct irq_affinity_desc *affinity);
856 			   const struct irq_affinity_desc *affinity);
863 	irq_alloc_descs(-1, 0, 1, node)
869 	irq_alloc_descs(-1, from, 1, node)
872 	irq_alloc_descs(-1, from, cnt, node)
878 	devm_irq_alloc_descs(dev, -1, 0, 1, node)
884 	devm_irq_alloc_descs(dev, -1, from, 1, node)
887 	devm_irq_alloc_descs(dev, -1, from, cnt, node)
915  * struct irq_chip_regs - register offsets for struct irq_gci
935  * struct irq_chip_type - Generic interrupt chip instance for a flow type
936  * @chip:		The real interrupt chip which provides the callbacks
957  * struct irq_chip_generic - Generic irq chip data structure
968  * @irq_base:		Interrupt base nr for this chip
973  * @wake_enabled:	Interrupt can wakeup from suspend
974  * @wake_active:	Interrupt is marked as an wakeup from suspend source
981  * @chip_types:		Array of interrupt irq_chip_types
1013  * enum irq_gc_flags - Initialization flags for generic irq chips
1019  * @IRQ_GC_NO_MASK:		Do not calculate irq_data->mask
1020  * @IRQ_GC_BE_IO:		Use big-endian register accesses (default: LE)
1031  * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
1037  * @gc:			Array of pointers to generic interrupt chips
1112 	return container_of(d->chip, struct irq_chip_type, chip);  in irq_data_get_chip_type()
1115 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
1120 	raw_spin_lock(&gc->lock);  in irq_gc_lock()
1125 	raw_spin_unlock(&gc->lock);  in irq_gc_unlock()
1133  * The irqsave variants are for usage in non interrupt code. Do not use
1137 	raw_spin_lock_irqsave(&(gc)->lock, flags)
1140 	raw_spin_unlock_irqrestore(&(gc)->lock, flags)
1145 	if (gc->reg_writel)  in irq_reg_writel()
1146 		gc->reg_writel(val, gc->reg_base + reg_offset);  in irq_reg_writel()
1148 		writel(val, gc->reg_base + reg_offset);  in irq_reg_writel()
1154 	if (gc->reg_readl)  in irq_reg_readl()
1155 		return gc->reg_readl(gc->reg_base + reg_offset);  in irq_reg_readl()
1157 		return readl(gc->reg_base + reg_offset);  in irq_reg_readl()
1193  * Registers a generic IRQ handling function as the top-level IRQ handler in
1195  * architecture-specific interrupt handler.
1197  * Returns 0 on success, or -EBUSY if an IRQ handler has already been
1203  * Allows interrupt handlers to find the irqchip that's been registered as the
1204  * top-level IRQ handler.