Lines Matching defs:intel_iommu
519 struct intel_iommu { struct
520 void __iomem *reg; /* Pointer to hardware regs, virtual addr */
521 u64 reg_phys; /* physical address of hw register set */
522 u64 reg_size; /* size of hw register set */
523 u64 cap;
524 u64 ecap;
525 u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
526 raw_spinlock_t register_lock; /* protect register handling */
527 int seq_id; /* sequence id of the iommu */
528 int agaw; /* agaw of this iommu */
529 int msagaw; /* max sagaw of this iommu */
530 unsigned int irq, pr_irq;
531 u16 segment; /* PCI segment# */
532 unsigned char name[13]; /* Device Name */
535 unsigned long *domain_ids; /* bitmap of domains */
536 struct dmar_domain ***domains; /* ptr to domains */
537 spinlock_t lock; /* protect context, domain ids */
538 struct root_entry *root_entry; /* virtual address */
540 struct iommu_flush flush;
543 struct page_req_dsc *prq;
544 unsigned char prq_name[16]; /* Name for PRQ interrupt */
546 struct q_inval *qi; /* Queued invalidation info */
547 u32 *iommu_state; /* Store iommu states between suspend and resume.*/
550 struct ir_table *ir_table; /* Interrupt remapping info */
551 struct irq_domain *ir_domain;
552 struct irq_domain *ir_msi_domain;
554 struct iommu_device iommu; /* IOMMU core code handle */
555 int node;
579 struct intel_iommu *iommu; /* IOMMU used by this device */ argument