Lines Matching full:ram
187 #define HP_SDC_CMD_READ_RAM 0x00 /* Load from i8042 RAM (autoinc) */
197 #define HP_SDC_CMD_READ_D0 0xf0 /* Load from i8042 RAM location 0x70 */
198 #define HP_SDC_CMD_READ_D1 0xf1 /* Load from i8042 RAM location 0x71 */
199 #define HP_SDC_CMD_READ_D2 0xf2 /* Load from i8042 RAM location 0x72 */
200 #define HP_SDC_CMD_READ_D3 0xf3 /* Load from i8042 RAM location 0x73 */
201 #define HP_SDC_CMD_READ_VT1 0xf4 /* Load from i8042 RAM location 0x74 */
202 #define HP_SDC_CMD_READ_VT2 0xf5 /* Load from i8042 RAM location 0x75 */
203 #define HP_SDC_CMD_READ_VT3 0xf6 /* Load from i8042 RAM location 0x76 */
204 #define HP_SDC_CMD_READ_VT4 0xf7 /* Load from i8042 RAM location 0x77 */
205 #define HP_SDC_CMD_READ_KBN 0xf8 /* Load from i8042 RAM location 0x78 */
206 #define HP_SDC_CMD_READ_KBC 0xf9 /* Load from i8042 RAM location 0x79 */
207 #define HP_SDC_CMD_READ_LPS 0xfa /* Load from i8042 RAM location 0x7a */
208 #define HP_SDC_CMD_READ_LPC 0xfb /* Load from i8042 RAM location 0x7b */
209 #define HP_SDC_CMD_READ_RSV 0xfc /* Load from i8042 RAM location 0x7c */
210 #define HP_SDC_CMD_READ_LPR 0xfd /* Load from i8042 RAM location 0x7d */
211 #define HP_SDC_CMD_READ_XTD 0xfe /* Load from i8042 RAM location 0x7e */
212 #define HP_SDC_CMD_READ_STR 0xff /* Load from i8042 RAM location 0x7f */
225 #define HP_SDC_CMD_SET_D0 0xe0 /* Load to i8042 RAM location 0x70 */
226 #define HP_SDC_CMD_SET_D1 0xe1 /* Load to i8042 RAM location 0x71 */
227 #define HP_SDC_CMD_SET_D2 0xe2 /* Load to i8042 RAM location 0x72 */
228 #define HP_SDC_CMD_SET_D3 0xe3 /* Load to i8042 RAM location 0x73 */
229 #define HP_SDC_CMD_SET_VT1 0xe4 /* Load to i8042 RAM location 0x74 */
230 #define HP_SDC_CMD_SET_VT2 0xe5 /* Load to i8042 RAM location 0x75 */
231 #define HP_SDC_CMD_SET_VT3 0xe6 /* Load to i8042 RAM location 0x76 */
232 #define HP_SDC_CMD_SET_VT4 0xe7 /* Load to i8042 RAM location 0x77 */
233 #define HP_SDC_CMD_SET_KBN 0xe8 /* Load to i8042 RAM location 0x78 */
234 #define HP_SDC_CMD_SET_KBC 0xe9 /* Load to i8042 RAM location 0x79 */
235 #define HP_SDC_CMD_SET_LPS 0xea /* Load to i8042 RAM location 0x7a */
236 #define HP_SDC_CMD_SET_LPC 0xeb /* Load to i8042 RAM location 0x7b */
237 #define HP_SDC_CMD_SET_RSV 0xec /* Load to i8042 RAM location 0x7c */
238 #define HP_SDC_CMD_SET_LPR 0xed /* Load to i8042 RAM location 0x7d */
239 #define HP_SDC_CMD_SET_XTD 0xee /* Load to i8042 RAM location 0x7e */
240 #define HP_SDC_CMD_SET_STR 0xef /* Load to i8042 RAM location 0x7f */
242 #define HP_SDC_CMD_DO_RTCW 0xc2 /* i8042 RAM 0x70 --> RTC */
244 #define HP_SDC_CMD_DO_BEEP 0xc4 /* i8042 RAM 0x70-74 --> beeper,VT3 */
245 #define HP_SDC_CMD_DO_HIL 0xc5 /* i8042 RAM 0x70-73 -->