Lines Matching refs:__be32
218 __be32 cdozsr; /* 0x0004 Core Doze Status Register */
220 __be32 cdozcr; /* 0x000c Core Doze Control Register */
222 __be32 cnapsr; /* 0x0014 Core Nap Status Register */
224 __be32 cnapcr; /* 0x001c Core Nap Control Register */
226 __be32 cdozpsr; /* 0x0024 Core Doze Previous Status Register */
228 __be32 cnappsr; /* 0x002c Core Nap Previous Status Register */
230 __be32 cwaitsr; /* 0x0034 Core Wait Status Register */
232 __be32 cwdtdsr; /* 0x003c Core Watchdog Detect Status Register */
233 __be32 powmgtcsr; /* 0x0040 PM Control&Status Register */
236 __be32 ippdexpcr; /* 0x0050 IP Powerdown Exception Control Register */
238 __be32 cpmimr; /* 0x0064 Core PM IRQ Mask Register */
240 __be32 cpmcimr; /* 0x006c Core PM Critical IRQ Mask Register */
242 __be32 cpmmcmr; /* 0x0074 Core PM Machine Check Mask Register */
244 __be32 cpmnmimr; /* 0x007c Core PM NMI Mask Register */
246 __be32 ctbenr; /* 0x0084 Core Time Base Enable Register */
248 __be32 ctbckselr; /* 0x008c Core Time Base Clock Select Register */
250 __be32 ctbhltcr; /* 0x0094 Core Time Base Halt Control Register */
252 __be32 cmcpmaskcr; /* 0x00a4 Core Machine Check Mask Register */
257 __be32 tph10sr0; /* Thread PH10 Status Register */
259 __be32 tph10setr0; /* Thread PH10 Set Control Register */
261 __be32 tph10clrr0; /* Thread PH10 Clear Control Register */
263 __be32 tph10psr0; /* Thread PH10 Previous Status Register */
265 __be32 twaitsr0; /* Thread Wait Status Register */
267 __be32 pcph15sr; /* Physical Core PH15 Status Register */
268 __be32 pcph15setr; /* Physical Core PH15 Set Control Register */
269 __be32 pcph15clrr; /* Physical Core PH15 Clear Control Register */
270 __be32 pcph15psr; /* Physical Core PH15 Prev Status Register */
272 __be32 pcph20sr; /* Physical Core PH20 Status Register */
273 __be32 pcph20setr; /* Physical Core PH20 Set Control Register */
274 __be32 pcph20clrr; /* Physical Core PH20 Clear Control Register */
275 __be32 pcph20psr; /* Physical Core PH20 Prev Status Register */
276 __be32 pcpw20sr; /* Physical Core PW20 Status Register */
278 __be32 pcph30sr; /* Physical Core PH30 Status Register */
279 __be32 pcph30setr; /* Physical Core PH30 Set Control Register */
280 __be32 pcph30clrr; /* Physical Core PH30 Clear Control Register */
281 __be32 pcph30psr; /* Physical Core PH30 Prev Status Register */
283 __be32 ippwrgatecr; /* IP Power Gating Control Register */
285 __be32 powmgtcsr; /* Power Management Control & Status Reg */
290 __be32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */
292 __be32 tpmimr0; /* Thread PM Interrupt Mask Reg */
294 __be32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */
296 __be32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */
298 __be32 tpmnmimr0; /* Thread PM NMI Mask Reg */
300 __be32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */
301 __be32 pctbenr; /* Physical Core Time Base Enable Reg */
302 __be32 pctbclkselr; /* Physical Core Time Base Clock Select */
303 __be32 tbclkdivr; /* Time Base Clock Divider Register */
305 __be32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */
306 __be32 clpcl10sr; /* Cluster PCL10 Status Register */
307 __be32 clpcl10setr; /* Cluster PCL30 Set Control Register */
308 __be32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */
309 __be32 clpcl10psr; /* Cluster PCL30 Prev Status Register */
310 __be32 cddslpsetr; /* Core Domain Deep Sleep Set Register */
311 __be32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */
312 __be32 cdpwroksetr; /* Core Domain Power OK Set Register */
313 __be32 cdpwrokclrr; /* Core Domain Power OK Clear Register */
314 __be32 cdpwrensr; /* Core Domain Power Enable Status Register */
315 __be32 cddslsr; /* Core Domain Deep Sleep Status Register */
317 __be32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */