962 	union pll_cntl_u pll_cntl;  member
1066 	w100_pwr_state.pll_cntl.f.pll_pwdn = 0x0;     /* power down */  in w100_pll_adjust()
1067 	w100_pwr_state.pll_cntl.f.pll_reset = 0x0;    /* not reset */  in w100_pll_adjust()
1068 	w100_pwr_state.pll_cntl.f.pll_tcpoff = 0x1;   /* Hi-Z */  in w100_pll_adjust()
1069 	w100_pwr_state.pll_cntl.f.pll_pvg = 0x0;      /* VCO gain = 0 */  in w100_pll_adjust()
1070 	w100_pwr_state.pll_cntl.f.pll_vcofr = 0x0;    /* VCO frequency range control = off */  in w100_pll_adjust()
1071 	w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0;  /* current offset inside VCO = 0 */  in w100_pll_adjust()
1072 	w100_pwr_state.pll_cntl.f.pll_ring_off = 0x0;  in w100_pll_adjust()
1080 		w100_pwr_state.pll_cntl.f.pll_dactal = 0xd;  in w100_pll_adjust()
1081 		writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);  in w100_pll_adjust()
1086 			w100_pwr_state.pll_cntl.f.pll_dactal = 0x7;  in w100_pll_adjust()
1087 			writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);  in w100_pll_adjust()
1093 			if ((w100_pwr_state.pll_cntl.f.pll_vcofr == 0x0) &&  in w100_pll_adjust()
1094 				((w100_pwr_state.pll_cntl.f.pll_pvg == 0x7) ||  in w100_pll_adjust()
1095 				(w100_pwr_state.pll_cntl.f.pll_ioffset == 0x0))) {  in w100_pll_adjust()
1097 				w100_pwr_state.pll_cntl.f.pll_vcofr = 0x1;  in w100_pll_adjust()
1098 				w100_pwr_state.pll_cntl.f.pll_pvg = 0x0;  in w100_pll_adjust()
1099 				w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0;  in w100_pll_adjust()
1103 		if ((w100_pwr_state.pll_cntl.f.pll_ioffset) < 0x3) {  in w100_pll_adjust()
1104 			w100_pwr_state.pll_cntl.f.pll_ioffset += 0x1;  in w100_pll_adjust()
1105 		} else if ((w100_pwr_state.pll_cntl.f.pll_pvg) < 0x7) {  in w100_pll_adjust()
1106 			w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0;  in w100_pll_adjust()
1107 			w100_pwr_state.pll_cntl.f.pll_pvg += 0x1;  in w100_pll_adjust()
1126 	w100_pwr_state.pll_cntl.f.pll_dactal = 0xa;  in w100_pll_calibration()
1127 	writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);  in w100_pll_calibration()
1132 	w100_pwr_state.pll_cntl.f.pll_tcpoff = 0x0;  /* normal */  in w100_pll_calibration()
1133 	writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);  in w100_pll_calibration()
1136 	w100_pwr_state.pll_cntl.f.pll_dactal = 0x0;  in w100_pll_calibration()
1137 	writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);  in w100_pll_calibration()
1240 	w100_pwr_state.pll_cntl.f.pll_pwdn = 0x1;  in w100_pwm_setup()
1241 	w100_pwr_state.pll_cntl.f.pll_reset = 0x1;  in w100_pwm_setup()
1242 	w100_pwr_state.pll_cntl.f.pll_pm_en = 0x0;  in w100_pwm_setup()
1243 	w100_pwr_state.pll_cntl.f.pll_mode = 0x0;  /* uses VCO clock */  in w100_pwm_setup()
1244 	w100_pwr_state.pll_cntl.f.pll_refclk_sel = 0x0;  in w100_pwm_setup()
1245 	w100_pwr_state.pll_cntl.f.pll_fbclk_sel = 0x0;  in w100_pwm_setup()
1246 	w100_pwr_state.pll_cntl.f.pll_tcpoff = 0x0;  in w100_pwm_setup()
1247 	w100_pwr_state.pll_cntl.f.pll_pcp = 0x4;  in w100_pwm_setup()
1248 	w100_pwr_state.pll_cntl.f.pll_pvg = 0x0;  in w100_pwm_setup()
1249 	w100_pwr_state.pll_cntl.f.pll_vcofr = 0x0;  in w100_pwm_setup()
1250 	w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0;  in w100_pwm_setup()
1251 	w100_pwr_state.pll_cntl.f.pll_pecc_mode = 0x0;  in w100_pwm_setup()
1252 	w100_pwr_state.pll_cntl.f.pll_pecc_scon = 0x0;  in w100_pwm_setup()
1253 	w100_pwr_state.pll_cntl.f.pll_dactal = 0x0;  /* Hi-Z */  in w100_pwm_setup()
1254 	w100_pwr_state.pll_cntl.f.pll_cp_clip = 0x3;  in w100_pwm_setup()
1255 	w100_pwr_state.pll_cntl.f.pll_conf = 0x2;  in w100_pwm_setup()
1256 	w100_pwr_state.pll_cntl.f.pll_mbctrl = 0x2;  in w100_pwm_setup()
1257 	w100_pwr_state.pll_cntl.f.pll_ring_off = 0x0;  in w100_pwm_setup()
1258 	writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);  in w100_pwm_setup()