123 	tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));  in dmafetch_set_fmt()
126 	writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));  in dmafetch_set_fmt()
167 	tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));  in dmafetch_onoff()
170 	writel(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));  in dmafetch_onoff()
178 	tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));  in path_enabledisable()
183 	writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));  in path_enabledisable()
258 	tmp = readl_relaxed(ctrl_regs(path) + intf_ctrl(path->id)) & 0x1;  in path_set_mode()
263 	writel_relaxed(tmp, ctrl_regs(path) + intf_ctrl(path->id));  in path_set_mode()
266 	tmp = readl_relaxed(ctrl_regs(path) + intf_rbswap_ctrl(path->id)) &  in path_set_mode()
269 	writel_relaxed(tmp, ctrl_regs(path) + intf_rbswap_ctrl(path->id));  in path_set_mode()
299 	tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));  in path_set_mode()
302 	writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));  in path_set_mode()
346 		tmp = readl_relaxed(ctrl_regs(path) + SPU_IOPAD_CONTROL);  in path_set_default()
349 		writel_relaxed(tmp, ctrl_regs(path) + SPU_IOPAD_CONTROL);  in path_set_default()
353 	tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));  in path_set_default()
356 	writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));  in path_set_default()
366 	writel_relaxed(dma_ctrl1, ctrl_regs(path) + dma_ctrl(1, path->id));  in path_set_default()
379 	tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));  in path_set_default()
383 	writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));  in path_set_default()