Lines Matching refs:dram_ctrl
898 outreg(dram_ctrl, GC_DCTL_IOCONT1_IOCONT0, GC_EVB_DCTL_IOCONT1_IOCONT0); in init_dram_ctrl()
901 outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD); in init_dram_ctrl()
902 outreg(dram_ctrl, GC_DCTL_SETTIME1_EMODE, GC_EVB_DCTL_SETTIME1_EMODE); in init_dram_ctrl()
903 outreg(dram_ctrl, GC_DCTL_REFRESH_SETTIME2, in init_dram_ctrl()
905 outreg(dram_ctrl, GC_DCTL_RSV2_RSV1, GC_EVB_DCTL_RSV2_RSV1); in init_dram_ctrl()
906 outreg(dram_ctrl, GC_DCTL_DDRIF2_DDRIF1, GC_EVB_DCTL_DDRIF2_DDRIF1); in init_dram_ctrl()
907 outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES); in init_dram_ctrl()
910 while ((inreg(dram_ctrl, GC_DCTL_RSV0_STATES) & GC_DCTL_STATES_MSK)) { in init_dram_ctrl()
917 outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD_AFT_RST); in init_dram_ctrl()
918 outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES_AFT_RST); in init_dram_ctrl()
933 par->dram_ctrl = par->mmio_base + MB86297_DRAMCTRL_BASE; in carmine_init()