410 		OUTREG(DSPABASE, offset);  in intelfbhw_pan_display()
432 	OUTREG(DSPACNTR, tmp);  in intelfbhw_do_blank()
435 	OUTREG(DSPABASE, tmp);  in intelfbhw_do_blank()
467 	OUTREG(ADPA, tmp);  in intelfbhw_do_blank()
511 	OUTREG(palette_reg + (regno << 2),  in intelfbhw_setcolreg()
1298 	OUTREG(VGACNTRL, tmp);  in intelfbhw_program_mode()
1355 	OUTREG(pipe_conf_reg, tmp);  in intelfbhw_program_mode()
1367 			OUTREG(pipe_conf_reg, tmp);  in intelfbhw_program_mode()
1371 	OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);  in intelfbhw_program_mode()
1376 	OUTREG(DSPACNTR, tmp);  in intelfbhw_program_mode()
1379 	OUTREG(DSPBCNTR, tmp);  in intelfbhw_program_mode()
1384 	OUTREG(DVOB, INREG(DVOB) & ~PORT_ENABLE);  in intelfbhw_program_mode()
1385 	OUTREG(DVOC, INREG(DVOC) & ~PORT_ENABLE);  in intelfbhw_program_mode()
1386 	OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);  in intelfbhw_program_mode()
1392 	OUTREG(ADPA, tmp);  in intelfbhw_program_mode()
1395 	OUTREG(0x61204, 0xabcd0000);  in intelfbhw_program_mode()
1400 	OUTREG(dpll_reg, tmp);  in intelfbhw_program_mode()
1403 	OUTREG(fp0_reg, *fp0);  in intelfbhw_program_mode()
1404 	OUTREG(fp1_reg, *fp1);  in intelfbhw_program_mode()
1407 	OUTREG(dpll_reg, *dpll);  in intelfbhw_program_mode()
1410 	OUTREG(DVOB, hw->dvob);  in intelfbhw_program_mode()
1411 	OUTREG(DVOC, hw->dvoc);  in intelfbhw_program_mode()
1414 	OUTREG(0x61204, 0x00000000);  in intelfbhw_program_mode()
1417 	OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);  in intelfbhw_program_mode()
1418 	OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);  in intelfbhw_program_mode()
1421 	OUTREG(hsync_reg, *hs);  in intelfbhw_program_mode()
1422 	OUTREG(hblank_reg, *hb);  in intelfbhw_program_mode()
1423 	OUTREG(htotal_reg, *ht);  in intelfbhw_program_mode()
1424 	OUTREG(vsync_reg, *vs);  in intelfbhw_program_mode()
1425 	OUTREG(vblank_reg, *vb);  in intelfbhw_program_mode()
1426 	OUTREG(vtotal_reg, *vt);  in intelfbhw_program_mode()
1427 	OUTREG(src_size_reg, *ss);  in intelfbhw_program_mode()
1432 		OUTREG(pipe_stat_reg, 0xFFFF | PIPESTAT_FLD_EVT_ODD_EN);  in intelfbhw_program_mode()
1435 		OUTREG(pipe_stat_reg, 0xFFFF | PIPESTAT_FLD_EVT_EVEN_EN);  in intelfbhw_program_mode()
1438 		OUTREG(pipe_stat_reg, 0xFFFF); /* clear all status bits only */  in intelfbhw_program_mode()
1441 	OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);  in intelfbhw_program_mode()
1447 	OUTREG(ADPA, tmp);  in intelfbhw_program_mode()
1459 			OUTREG(DSPACNTR, tmp);  in intelfbhw_program_mode()
1460 			OUTREG(DSPACNTR,  in intelfbhw_program_mode()
1466 	OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);  in intelfbhw_program_mode()
1467 	OUTREG(DSPASTRIDE, hw->disp_a_stride);  in intelfbhw_program_mode()
1468 	OUTREG(DSPABASE, hw->disp_a_base);  in intelfbhw_program_mode()
1474 		OUTREG(DSPACNTR, tmp);  in intelfbhw_program_mode()
1475 		OUTREG(DSPABASE, hw->disp_a_base);  in intelfbhw_program_mode()
1594 		OUTREG(FENCE + (i << 2), 0);  in reset_state()
1607 	OUTREG(PRI_RING_LENGTH, 0);  in reset_state()
1608 	OUTREG(PRI_RING_HEAD, 0);  in reset_state()
1609 	OUTREG(PRI_RING_TAIL, 0);  in reset_state()
1610 	OUTREG(PRI_RING_START, 0);  in reset_state()
1644 	OUTREG(PRI_RING_LENGTH, 0);  in intelfbhw_2d_start()
1645 	OUTREG(PRI_RING_TAIL, 0);  in intelfbhw_2d_start()
1646 	OUTREG(PRI_RING_HEAD, 0);  in intelfbhw_2d_start()
1648 	OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);  in intelfbhw_2d_start()
1649 	OUTREG(PRI_RING_LENGTH,  in intelfbhw_2d_start()
1852 		OUTREG(CURSOR_A_CONTROL, tmp);  in intelfbhw_cursor_init()
1853 		OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);  in intelfbhw_cursor_init()
1859 		OUTREG(CURSOR_CONTROL, tmp);  in intelfbhw_cursor_init()
1860 		OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);  in intelfbhw_cursor_init()
1863 		OUTREG(CURSOR_SIZE, tmp);  in intelfbhw_cursor_init()
1882 		OUTREG(CURSOR_A_CONTROL, tmp);  in intelfbhw_cursor_hide()
1884 		OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);  in intelfbhw_cursor_hide()
1888 		OUTREG(CURSOR_CONTROL, tmp);  in intelfbhw_cursor_hide()
1911 		OUTREG(CURSOR_A_CONTROL, tmp);  in intelfbhw_cursor_show()
1913 		OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);  in intelfbhw_cursor_show()
1917 		OUTREG(CURSOR_CONTROL, tmp);  in intelfbhw_cursor_show()
1937 	OUTREG(CURSOR_A_POSITION, tmp);  in intelfbhw_cursor_setpos()
1940 		OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);  in intelfbhw_cursor_setpos()
1949 	OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);  in intelfbhw_cursor_setcolor()
1950 	OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);  in intelfbhw_cursor_setcolor()
1951 	OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);  in intelfbhw_cursor_setcolor()
1952 	OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);  in intelfbhw_cursor_setcolor()
2024 	OUTREG(PIPEASTAT, INREG(PIPEASTAT));  in intelfbhw_irq()
2029 		OUTREG(DSPABASE, dinfo->vsync.pan_offset);  in intelfbhw_irq()
2074 			OUTREG(DSPABASE, dinfo->vsync.pan_offset);  in intelfbhw_disable_irq()