Lines Matching refs:OUTREG
552 OUTREG( MC_IND_INDEX, indx | MC_IND_INDEX__MC_IND_WR_EN); in OUTMC()
553 OUTREG( MC_IND_DATA, value); in OUTMC()
558 OUTREG( MC_IND_INDEX, indx); in INMC()
703 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]); in radeon_pm_restore_regs()
704 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]); in radeon_pm_restore_regs()
705 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]); in radeon_pm_restore_regs()
706 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]); in radeon_pm_restore_regs()
707 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]); in radeon_pm_restore_regs()
708 OUTREG(CNFG_MEMSIZE, rinfo->video_ram); in radeon_pm_restore_regs()
710 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]); in radeon_pm_restore_regs()
711 OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]); in radeon_pm_restore_regs()
712 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11]); in radeon_pm_restore_regs()
713 OUTREG(LVDS_PLL_CNTL,rinfo->save_regs[12]); in radeon_pm_restore_regs()
714 OUTREG(TV_DAC_CNTL, rinfo->save_regs[13]); in radeon_pm_restore_regs()
715 OUTREG(BUS_CNTL1, rinfo->save_regs[14]); in radeon_pm_restore_regs()
716 OUTREG(CRTC_OFFSET_CNTL, rinfo->save_regs[15]); in radeon_pm_restore_regs()
717 OUTREG(AGP_CNTL, rinfo->save_regs[16]); in radeon_pm_restore_regs()
718 OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[17]); in radeon_pm_restore_regs()
719 OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[18]); in radeon_pm_restore_regs()
722 OUTREG(GPIOPAD_A, rinfo->save_regs[19]); in radeon_pm_restore_regs()
723 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]); in radeon_pm_restore_regs()
724 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]); in radeon_pm_restore_regs()
725 OUTREG(ZV_LCDPAD_A, rinfo->save_regs[22]); in radeon_pm_restore_regs()
726 OUTREG(ZV_LCDPAD_EN, rinfo->save_regs[23]); in radeon_pm_restore_regs()
727 OUTREG(ZV_LCDPAD_MASK, rinfo->save_regs[24]); in radeon_pm_restore_regs()
728 OUTREG(GPIO_VGA_DDC, rinfo->save_regs[25]); in radeon_pm_restore_regs()
729 OUTREG(GPIO_DVI_DDC, rinfo->save_regs[26]); in radeon_pm_restore_regs()
730 OUTREG(GPIO_MONID, rinfo->save_regs[27]); in radeon_pm_restore_regs()
731 OUTREG(GPIO_CRT2_DDC, rinfo->save_regs[28]); in radeon_pm_restore_regs()
736 OUTREG(GPIOPAD_MASK, 0x0001ffff); in radeon_pm_disable_iopad()
737 OUTREG(GPIOPAD_EN, 0x00000400); in radeon_pm_disable_iopad()
738 OUTREG(GPIOPAD_A, 0x00000000); in radeon_pm_disable_iopad()
739 OUTREG(ZV_LCDPAD_MASK, 0x00000000); in radeon_pm_disable_iopad()
740 OUTREG(ZV_LCDPAD_EN, 0x00000000); in radeon_pm_disable_iopad()
741 OUTREG(ZV_LCDPAD_A, 0x00000000); in radeon_pm_disable_iopad()
742 OUTREG(GPIO_VGA_DDC, 0x00030000); in radeon_pm_disable_iopad()
743 OUTREG(GPIO_DVI_DDC, 0x00000000); in radeon_pm_disable_iopad()
744 OUTREG(GPIO_MONID, 0x00030000); in radeon_pm_disable_iopad()
745 OUTREG(GPIO_CRT2_DDC, 0x00000000); in radeon_pm_disable_iopad()
789 OUTREG(BUS_CNTL1, reg); in radeon_pm_low_current()
803 OUTREG(TV_DAC_CNTL, reg); in radeon_pm_low_current()
807 OUTREG(TMDS_TRANSMITTER_CNTL, reg); in radeon_pm_low_current()
811 OUTREG(DAC_CNTL, reg); in radeon_pm_low_current()
815 OUTREG(DAC_CNTL2, reg); in radeon_pm_low_current()
819 OUTREG(TV_DAC_CNTL, reg); in radeon_pm_low_current()
911 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & in radeon_pm_setup_for_suspend()
964 OUTREG(BUS_CNTL1, INREG(BUS_CNTL1) | BUS_CNTL1__AGPCLK_VALID); in radeon_pm_setup_for_suspend()
965 OUTREG(BUS_CNTL1, in radeon_pm_setup_for_suspend()
969 OUTREG(BUS_CNTL1, INREG(BUS_CNTL1)); in radeon_pm_setup_for_suspend()
970 OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & ~0x4000) | 0x8000); in radeon_pm_setup_for_suspend()
975 OUTREG(CRTC_OFFSET_CNTL, (INREG(CRTC_OFFSET_CNTL) in radeon_pm_setup_for_suspend()
983 OUTREG(AGP_CNTL, in radeon_pm_setup_for_suspend()
1008 OUTREG(DISP_MISC_CNTL, disp_mis_cntl); in radeon_pm_setup_for_suspend()
1030 OUTREG(DISP_PWR_MAN, disp_pwr_man); in radeon_pm_setup_for_suspend()
1048 OUTREG(DISP_PWR_MAN, disp_pwr_man); in radeon_pm_setup_for_suspend()
1051 OUTREG( CRTC_GEN_CNTL, (INREG( CRTC_GEN_CNTL) & ~CRTC_GEN_CNTL__CRTC_EN) in radeon_pm_setup_for_suspend()
1053 OUTREG( CRTC2_GEN_CNTL, (INREG( CRTC2_GEN_CNTL) & ~CRTC2_GEN_CNTL__CRTC2_EN) in radeon_pm_setup_for_suspend()
1110 OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode); in radeon_pm_program_mode_reg()
1115 OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode); in radeon_pm_program_mode_reg()
1120 OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode); in radeon_pm_program_mode_reg()
1261 OUTREG( CRTC_MORE_CNTL, 0); in radeon_pm_full_reset_sdram()
1262 OUTREG( FP_GEN_CNTL, 0); in radeon_pm_full_reset_sdram()
1263 OUTREG( FP2_GEN_CNTL,0); in radeon_pm_full_reset_sdram()
1265 OUTREG( CRTC_GEN_CNTL, (crtcGenCntl | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B) ); in radeon_pm_full_reset_sdram()
1266 OUTREG( CRTC2_GEN_CNTL, (crtcGenCntl2 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B) ); in radeon_pm_full_reset_sdram()
1288 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl in radeon_pm_full_reset_sdram()
1309 OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg); in radeon_pm_full_reset_sdram()
1319 OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg); in radeon_pm_full_reset_sdram()
1325 OUTREG(MEM_REFRESH_CNTL, memRefreshCntl); in radeon_pm_full_reset_sdram()
1334 OUTREG(MEM_REFRESH_CNTL, memRefreshCntl in radeon_pm_full_reset_sdram()
1339 OUTREG(MEM_SDRAM_MODE_REG, in radeon_pm_full_reset_sdram()
1346 OUTREG(MEM_SDRAM_MODE_REG, in radeon_pm_full_reset_sdram()
1349 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl); in radeon_pm_full_reset_sdram()
1356 OUTREG( EXT_MEM_CNTL, memRefreshCntl | (1 << 20)); in radeon_pm_full_reset_sdram()
1359 OUTREG( MEM_SDRAM_MODE_REG, in radeon_pm_full_reset_sdram()
1377 OUTREG( MEM_SDRAM_MODE_REG, in radeon_pm_full_reset_sdram()
1380 OUTREG(EXT_MEM_CNTL, memRefreshCntl); in radeon_pm_full_reset_sdram()
1388 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl in radeon_pm_full_reset_sdram()
1392 OUTREG( MEM_SDRAM_MODE_REG, in radeon_pm_full_reset_sdram()
1418 OUTREG( MEM_SDRAM_MODE_REG, in radeon_pm_full_reset_sdram()
1421 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl); in radeon_pm_full_reset_sdram()
1424 OUTREG( CRTC_GEN_CNTL, crtcGenCntl); in radeon_pm_full_reset_sdram()
1425 OUTREG( CRTC2_GEN_CNTL, crtcGenCntl2); in radeon_pm_full_reset_sdram()
1426 OUTREG( FP_GEN_CNTL, fp_gen_cntl); in radeon_pm_full_reset_sdram()
1427 OUTREG( FP2_GEN_CNTL, fp2_gen_cntl); in radeon_pm_full_reset_sdram()
1429 OUTREG( CRTC_MORE_CNTL, crtc_more_cntl); in radeon_pm_full_reset_sdram()
1443 OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~PAD_MANUAL_OVERRIDE); in radeon_pm_reset_pad_ctlr_strength()
1564 OUTREG(VGA_DDA_ON_OFF, r2ec); in radeon_pm_m10_disable_spread_spectrum()
1578 OUTREG(VGA_DDA_ON_OFF, r2ec); in radeon_pm_m10_disable_spread_spectrum()
1591 OUTREG(VGA_DDA_ON_OFF, r2ec); in radeon_pm_m10_enable_lvds_spread_spectrum()
1610 OUTREG(VGA_DDA_ON_OFF, r2ec); in radeon_pm_m10_enable_lvds_spread_spectrum()
1615 OUTREG(LVDS_GEN_CNTL, tmp | LVDS_EN); in radeon_pm_m10_enable_lvds_spread_spectrum()
1621 OUTREG(LVDS_PLL_CNTL, tmp); in radeon_pm_m10_enable_lvds_spread_spectrum()
1693 OUTREG(MC_CNTL, rinfo->save_regs[46]); in radeon_pm_m10_reconfigure_mc()
1694 OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]); in radeon_pm_m10_reconfigure_mc()
1695 OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]); in radeon_pm_m10_reconfigure_mc()
1696 OUTREG(MEM_SDRAM_MODE_REG, in radeon_pm_m10_reconfigure_mc()
1698 OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]); in radeon_pm_m10_reconfigure_mc()
1699 OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]); in radeon_pm_m10_reconfigure_mc()
1700 OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]); in radeon_pm_m10_reconfigure_mc()
1701 OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]); in radeon_pm_m10_reconfigure_mc()
1702 OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]); in radeon_pm_m10_reconfigure_mc()
1703 OUTREG(MC_DEBUG, rinfo->save_regs[53]); in radeon_pm_m10_reconfigure_mc()
1721 OUTREG(MC_IND_INDEX, 0); in radeon_pm_m10_reconfigure_mc()
1729 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]); in radeon_reinitialize_M10()
1730 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]); in radeon_reinitialize_M10()
1731 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]); in radeon_reinitialize_M10()
1732 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]); in radeon_reinitialize_M10()
1733 OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]); in radeon_reinitialize_M10()
1734 OUTREG(CNFG_MEMSIZE, rinfo->video_ram); in radeon_reinitialize_M10()
1735 OUTREG(BUS_CNTL, rinfo->save_regs[36]); in radeon_reinitialize_M10()
1736 OUTREG(BUS_CNTL1, rinfo->save_regs[14]); in radeon_reinitialize_M10()
1737 OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]); in radeon_reinitialize_M10()
1738 OUTREG(FCP_CNTL, rinfo->save_regs[38]); in radeon_reinitialize_M10()
1739 OUTREG(RBBM_CNTL, rinfo->save_regs[39]); in radeon_reinitialize_M10()
1740 OUTREG(DAC_CNTL, rinfo->save_regs[40]); in radeon_reinitialize_M10()
1741 OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8); in radeon_reinitialize_M10()
1742 OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8); in radeon_reinitialize_M10()
1745 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE); in radeon_reinitialize_M10()
1758 OUTREG(SURFACE_CNTL, 0); in radeon_reinitialize_M10()
1765 OUTREG(TV_DAC_CNTL, tmp); in radeon_reinitialize_M10()
1769 OUTREG(TV_DAC_CNTL, tmp); in radeon_reinitialize_M10()
1772 OUTREG(AGP_CNTL, rinfo->save_regs[16]); in radeon_reinitialize_M10()
1773 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]); in radeon_reinitialize_M10()
1774 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]); in radeon_reinitialize_M10()
1782 OUTREG(PAD_CTLR_MISC, rinfo->save_regs[56]); in radeon_reinitialize_M10()
1783 OUTREG(FW_CNTL, rinfo->save_regs[57]); in radeon_reinitialize_M10()
1784 OUTREG(HDP_DEBUG, rinfo->save_regs[96]); in radeon_reinitialize_M10()
1785 OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]); in radeon_reinitialize_M10()
1786 OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]); in radeon_reinitialize_M10()
1787 OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]); in radeon_reinitialize_M10()
1793 OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL) in radeon_reinitialize_M10()
1795 OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL) in radeon_reinitialize_M10()
1800 OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL) in radeon_reinitialize_M10()
1899 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20); in radeon_reinitialize_M10()
1901 OUTREG(PALETTE_30_DATA, 0x15555555); in radeon_reinitialize_M10()
1902 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20); in radeon_reinitialize_M10()
1905 OUTREG(PALETTE_30_DATA, 0x15555555); in radeon_reinitialize_M10()
1907 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20); in radeon_reinitialize_M10()
1911 OUTREG(FP_GEN_CNTL, rinfo->save_regs[82]); in radeon_reinitialize_M10()
1912 OUTREG(FP2_GEN_CNTL, rinfo->save_regs[83]); in radeon_reinitialize_M10()
1915 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] & in radeon_reinitialize_M10()
1917 OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000); in radeon_reinitialize_M10()
1919 OUTREG(DISP_OUTPUT_CNTL, rinfo->save_regs[86]); in radeon_reinitialize_M10()
1922 OUTREG(GPIOPAD_A, rinfo->save_regs[19]); in radeon_reinitialize_M10()
1923 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]); in radeon_reinitialize_M10()
1924 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]); in radeon_reinitialize_M10()
1931 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON); in radeon_reinitialize_M10()
1935 OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]); in radeon_reinitialize_M10()
1936 OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]); in radeon_reinitialize_M10()
1954 OUTREG(MC_CNTL, rinfo->save_regs[46]); in radeon_pm_m9p_reconfigure_mc()
1955 OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]); in radeon_pm_m9p_reconfigure_mc()
1956 OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]); in radeon_pm_m9p_reconfigure_mc()
1957 OUTREG(MEM_SDRAM_MODE_REG, in radeon_pm_m9p_reconfigure_mc()
1959 OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]); in radeon_pm_m9p_reconfigure_mc()
1960 OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]); in radeon_pm_m9p_reconfigure_mc()
1961 OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]); in radeon_pm_m9p_reconfigure_mc()
1962 OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]); in radeon_pm_m9p_reconfigure_mc()
1963 OUTREG(MC_DEBUG, rinfo->save_regs[53]); in radeon_pm_m9p_reconfigure_mc()
1964 OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]); in radeon_pm_m9p_reconfigure_mc()
1972 OUTREG(MC_IND_INDEX, 0); in radeon_pm_m9p_reconfigure_mc()
1973 OUTREG(CNFG_MEMSIZE, rinfo->video_ram); in radeon_pm_m9p_reconfigure_mc()
1983 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]); in radeon_reinitialize_M9P()
1984 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]); in radeon_reinitialize_M9P()
1985 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]); in radeon_reinitialize_M9P()
1986 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]); in radeon_reinitialize_M9P()
1987 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]); in radeon_reinitialize_M9P()
1988 OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]); in radeon_reinitialize_M9P()
1989 OUTREG(BUS_CNTL, rinfo->save_regs[36]); in radeon_reinitialize_M9P()
1990 OUTREG(BUS_CNTL1, rinfo->save_regs[14]); in radeon_reinitialize_M9P()
1991 OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]); in radeon_reinitialize_M9P()
1992 OUTREG(FCP_CNTL, rinfo->save_regs[38]); in radeon_reinitialize_M9P()
1993 OUTREG(RBBM_CNTL, rinfo->save_regs[39]); in radeon_reinitialize_M9P()
1995 OUTREG(DAC_CNTL, rinfo->save_regs[40]); in radeon_reinitialize_M9P()
1996 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE); in radeon_reinitialize_M9P()
2009 OUTREG(SURFACE_CNTL, 0); in radeon_reinitialize_M9P()
2016 OUTREG(TV_DAC_CNTL, tmp); in radeon_reinitialize_M9P()
2020 OUTREG(TV_DAC_CNTL, tmp); in radeon_reinitialize_M9P()
2024 OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]); in radeon_reinitialize_M9P()
2025 OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]); in radeon_reinitialize_M9P()
2026 OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]); in radeon_reinitialize_M9P()
2028 OUTREG(AGP_CNTL, rinfo->save_regs[16]); in radeon_reinitialize_M9P()
2029 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]); /* MacOS sets that to 0 !!! */ in radeon_reinitialize_M9P()
2030 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]); in radeon_reinitialize_M9P()
2037 OUTREG(FW_CNTL, rinfo->save_regs[57]); in radeon_reinitialize_M9P()
2040 OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL) in radeon_reinitialize_M9P()
2115 OUTREG(CRTC_GEN_CNTL, 0x04000000); in radeon_reinitialize_M9P()
2116 OUTREG(CRTC2_GEN_CNTL, 0x04000000); in radeon_reinitialize_M9P()
2117 OUTREG(FP_GEN_CNTL, 0x00004008); in radeon_reinitialize_M9P()
2118 OUTREG(FP2_GEN_CNTL, 0x00000008); in radeon_reinitialize_M9P()
2119 OUTREG(LVDS_GEN_CNTL, 0x08000008); in radeon_reinitialize_M9P()
2131 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20); in radeon_reinitialize_M9P()
2133 OUTREG(PALETTE_30_DATA, 0x15555555); in radeon_reinitialize_M9P()
2134 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20); in radeon_reinitialize_M9P()
2137 OUTREG(PALETTE_30_DATA, 0x15555555); in radeon_reinitialize_M9P()
2139 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20); in radeon_reinitialize_M9P()
2143 OUTREG(TV_MASTER_CNTL, rinfo->save_regs[88]); in radeon_reinitialize_M9P()
2144 OUTREG(TV_DAC_CNTL, rinfo->save_regs[13] | 0x07000000); in radeon_reinitialize_M9P()
2151 OUTREG(GPIOPAD_A, rinfo->save_regs[19]); in radeon_reinitialize_M9P()
2152 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]); in radeon_reinitialize_M9P()
2153 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]); in radeon_reinitialize_M9P()
2168 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] & in radeon_reinitialize_M9P()
2170 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_BLON); in radeon_reinitialize_M9P()
2171 OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000); in radeon_reinitialize_M9P()
2178 OUTREG(0x2ec, 0x6332a020); in radeon_reinitialize_M9P()
2193 OUTREG(0x2ec, 0x6332a3f0); in radeon_reinitialize_M9P()
2200 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON); in radeon_reinitialize_M9P()
2204 OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]); in radeon_reinitialize_M9P()
2205 OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]); in radeon_reinitialize_M9P()
2223 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
2224 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
2225 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
2226 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
2227 OUTREG(BUS_CNTL, rinfo->save_regs[36]);
2228 OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
2231 OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~0x10000);
2237 OUTREG(DISP_TEST_DEBUG_CNTL, INREG(DISP_TEST_DEBUG_CNTL) | 0x10000000);
2238 OUTREG(OV0_FLAG_CNTRL, INREG(OV0_FLAG_CNTRL) | 0x100);
2239 OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL));
2240 OUTREG(DAC_CNTL, 0xff00410a);
2241 OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL));
2242 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x4000);
2244 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
2245 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2246 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
2247 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2250 OUTREG(MC_IND_INDEX, 0);
2252 OUTREG(MC_IND_INDEX, 0);
2254 OUTREG(CRTC_MORE_CNTL, INREG(CRTC_MORE_CNTL));
2348 OUTREG(MC_IND_INDEX, 0);
2350 OUTREG(MC_IND_INDEX, 0);
2353 OUTREG(MC_IND_INDEX, 0);
2355 OUTREG(MC_IND_INDEX, 0);
2361 OUTREG(MEM_CNTL, 0x29002901);
2362 OUTREG(MEM_SDRAM_MODE_REG, 0x45320032); /* XXX use save_regs[35]? */
2363 OUTREG(EXT_MEM_CNTL, 0x1a394333);
2364 OUTREG(MEM_IO_CNTL_A1, 0x0aac0aac);
2365 OUTREG(MEM_INIT_LATENCY_TIMER, 0x34444444);
2366 OUTREG(MEM_REFRESH_CNTL, 0x1f1f7218); /* XXX or save_regs[42]? */
2367 OUTREG(MC_DEBUG, 0);
2368 OUTREG(MEM_IO_OE_CNTL, 0x04300430);
2371 OUTREG(MC_IND_INDEX, 0);
2373 OUTREG(MC_IND_INDEX, 0);
2375 OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
2380 OUTREG(TMDS_CNTL, 0x01000000); /* XXX ? */
2383 OUTREG(FP_GEN_CNTL, tmp);
2387 OUTREG(DISP_OUTPUT_CNTL, tmp);
2400 OUTREG(CRTC_MORE_CNTL, 0);
2403 OUTREG(CRTC_PITCH, 32);
2416 OUTREG(FP_GEN_CNTL, tmp);
2418 OUTREG(FP_GEN_CNTL, tmp);
2420 OUTREG(TMDS_TRANSMITTER_CNTL, tmp2);
2421 OUTREG(CRTC_MORE_CNTL, 0);
2425 OUTREG(CRTC_MORE_CNTL, tmp);
2431 OUTREG(CRTC_H_SYNC_STRT_WID, 0x008e0580);
2432 OUTREG(CRTC_H_TOTAL_DISP, 0x009f00d2);
2437 OUTREG(CRTC_V_SYNC_STRT_WID, 0x00830403);
2438 OUTREG(CRTC_V_TOTAL_DISP, 0x03ff0429);
2439 OUTREG(FP_CRTC_H_TOTAL_DISP, 0x009f0033);
2440 OUTREG(FP_H_SYNC_STRT_WID, 0x008e0080);
2441 OUTREG(CRT_CRTC_H_SYNC_STRT_WID, 0x008e0080);
2442 OUTREG(FP_CRTC_V_TOTAL_DISP, 0x03ff002a);
2443 OUTREG(FP_V_SYNC_STRT_WID, 0x00830004);
2444 OUTREG(CRT_CRTC_V_SYNC_STRT_WID, 0x00830004);
2445 OUTREG(FP_HORZ_VERT_ACTIVE, 0x009f03ff);
2446 OUTREG(FP_HORZ_STRETCH, 0);
2447 OUTREG(FP_VERT_STRETCH, 0);
2448 OUTREG(OVR_CLR, 0);
2449 OUTREG(OVR_WID_LEFT_RIGHT, 0);
2450 OUTREG(OVR_WID_TOP_BOTTOM, 0);
2464 OUTREG(CLOCK_CNTL_INDEX, tmp & 0xff);
2485 OUTREG(CRTC2_GEN_CNTL, c2gc);
2487 OUTREG(CRTC_GEN_CNTL, cgc);
2488 OUTREG(CRTC_EXT_CNTL, cec);
2489 OUTREG(CRTC_PITCH, 0xa0);
2490 OUTREG(CRTC_OFFSET, 0);
2491 OUTREG(CRTC_OFFSET_CNTL, 0);
2493 OUTREG(GRPH_BUFFER_CNTL, 0x20117c7c);
2494 OUTREG(GRPH2_BUFFER_CNTL, 0x00205c5c);
2498 OUTREG(0x2a8, 0x0000061b);
2500 OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
2503 OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
2506 OUTREG(FP_GEN_CNTL, tmp2);
2509 OUTREG(FP_GEN_CNTL, tmp2);
2511 OUTREG(CUR_HORZ_VERT_OFF, CUR_LOCK | 1);
2513 OUTREG(CUR_HORZ_VERT_POSN, 0xbfff0fff);
2515 OUTREG(CUR_OFFSET, 0);
2687 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_BL_MOD_EN)); in radeonfb_pci_suspend()
2689 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_EN | LVDS_ON)); in radeonfb_pci_suspend()
2690 OUTREG(LVDS_PLL_CNTL, (INREG(LVDS_PLL_CNTL) & ~30000) | 0x20000); in radeonfb_pci_suspend()
2692 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_DIGON)); in radeonfb_pci_suspend()
2885 OUTREG(TV_DAC_CNTL, INREG(TV_DAC_CNTL) | 0x07000000); in radeonfb_pm_init()