137 			tmp = INPLL(pllSCLK_CNTL);  in radeon_pm_disable_dynamic_mode()
142 		tmp = INPLL(pllMCLK_CNTL);  in radeon_pm_disable_dynamic_mode()
154                 tmp = INPLL(pllSCLK_CNTL);  in radeon_pm_disable_dynamic_mode()
168                 tmp = INPLL(pllSCLK_CNTL2);  in radeon_pm_disable_dynamic_mode()
174                 tmp = INPLL(pllSCLK_CNTL);  in radeon_pm_disable_dynamic_mode()
185                 tmp = INPLL(pllSCLK_MORE_CNTL);  in radeon_pm_disable_dynamic_mode()
190 		tmp = INPLL(pllMCLK_CNTL);  in radeon_pm_disable_dynamic_mode()
198                 tmp = INPLL(pllVCLK_ECP_CNTL);  in radeon_pm_disable_dynamic_mode()
204                 tmp = INPLL(pllPIXCLKS_CNTL);  in radeon_pm_disable_dynamic_mode()
226 	tmp = INPLL(pllSCLK_CNTL);  in radeon_pm_disable_dynamic_mode()
262 		tmp = INPLL(pllSCLK_CNTL2);  in radeon_pm_disable_dynamic_mode()
270 	tmp = INPLL(pllCLK_PIN_CNTL);  in radeon_pm_disable_dynamic_mode()
279 		tmp = INPLL(pllMCLK_CNTL);  in radeon_pm_disable_dynamic_mode()
287 		tmp = INPLL(pllMCLK_CNTL);  in radeon_pm_disable_dynamic_mode()
295 		tmp = INPLL(pllMCLK_MISC);  in radeon_pm_disable_dynamic_mode()
305 		tmp = INPLL(pllSCLK_MORE_CNTL);  in radeon_pm_disable_dynamic_mode()
313 	tmp = INPLL(pllPIXCLKS_CNTL);  in radeon_pm_disable_dynamic_mode()
324 	tmp = INPLL( pllVCLK_ECP_CNTL);  in radeon_pm_disable_dynamic_mode()
337                 tmp = INPLL(pllSCLK_CNTL);  in radeon_pm_enable_dynamic_mode()
352 		tmp = INPLL(pllSCLK_CNTL2);  in radeon_pm_enable_dynamic_mode()
361 		tmp = INPLL(pllSCLK_CNTL);  in radeon_pm_enable_dynamic_mode()
373 		tmp = INPLL(pllSCLK_MORE_CNTL);  in radeon_pm_enable_dynamic_mode()
380 		tmp = INPLL(pllVCLK_ECP_CNTL);  in radeon_pm_enable_dynamic_mode()
385 		tmp = INPLL(pllPIXCLKS_CNTL);  in radeon_pm_enable_dynamic_mode()
401 		tmp = INPLL(pllMCLK_MISC);  in radeon_pm_enable_dynamic_mode()
406 		tmp = INPLL(pllMCLK_CNTL);  in radeon_pm_enable_dynamic_mode()
420 			tmp = INPLL(pllMCLK_CNTL);  in radeon_pm_enable_dynamic_mode()
437 		tmp = INPLL(pllSCLK_CNTL);  in radeon_pm_enable_dynamic_mode()
443 		tmp = INPLL(pllSCLK_CNTL2);  in radeon_pm_enable_dynamic_mode()
452 	tmp = INPLL( pllCLK_PWRMGT_CNTL);  in radeon_pm_enable_dynamic_mode()
461 	tmp = INPLL(pllCLK_PIN_CNTL);  in radeon_pm_enable_dynamic_mode()
469 	tmp = INPLL(pllSCLK_CNTL);  in radeon_pm_enable_dynamic_mode()
486 		tmp = INPLL(pllSCLK_MORE_CNTL);  in radeon_pm_enable_dynamic_mode()
504 		tmp = INPLL(pllPLL_PWRMGT_CNTL);  in radeon_pm_enable_dynamic_mode()
510 	tmp = INPLL(pllPIXCLKS_CNTL);  in radeon_pm_enable_dynamic_mode()
521 	tmp = INPLL(pllVCLK_ECP_CNTL);  in radeon_pm_enable_dynamic_mode()
529 		tmp  = INPLL(pllMCLK_CNTL);  in radeon_pm_enable_dynamic_mode()
537 		tmp = INPLL(pllMCLK_MISC);  in radeon_pm_enable_dynamic_mode()
564 	rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL);  in radeon_pm_save_regs()
565 	rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL);  in radeon_pm_save_regs()
566 	rinfo->save_regs[2] = INPLL(MCLK_CNTL);  in radeon_pm_save_regs()
567 	rinfo->save_regs[3] = INPLL(SCLK_CNTL);  in radeon_pm_save_regs()
568 	rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL);  in radeon_pm_save_regs()
569 	rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL);  in radeon_pm_save_regs()
570 	rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL);  in radeon_pm_save_regs()
571 	rinfo->save_regs[7] = INPLL(MCLK_MISC);  in radeon_pm_save_regs()
572 	rinfo->save_regs[8] = INPLL(P2PLL_CNTL);  in radeon_pm_save_regs()
600 	rinfo->save_regs[34] = INPLL(SCLK_MORE_CNTL);  in radeon_pm_save_regs()
611 		rinfo->save_regs[43] = INPLL(pllSSPLL_CNTL);  in radeon_pm_save_regs()
612 		rinfo->save_regs[44] = INPLL(pllSSPLL_REF_DIV);  in radeon_pm_save_regs()
613 		rinfo->save_regs[45] = INPLL(pllSSPLL_DIV_0);  in radeon_pm_save_regs()
614 		rinfo->save_regs[90] = INPLL(pllSS_INT_CNTL);  in radeon_pm_save_regs()
615 		rinfo->save_regs[91] = INPLL(pllSS_TST_CNTL);  in radeon_pm_save_regs()
661 	rinfo->save_regs[73] = INPLL(pllMPLL_CNTL);  in radeon_pm_save_regs()
662 	rinfo->save_regs[74] = INPLL(pllSPLL_CNTL);  in radeon_pm_save_regs()
663 	rinfo->save_regs[75] = INPLL(pllMPLL_AUX_CNTL);  in radeon_pm_save_regs()
664 	rinfo->save_regs[76] = INPLL(pllSPLL_AUX_CNTL);  in radeon_pm_save_regs()
665 	rinfo->save_regs[77] = INPLL(pllM_SPLL_REF_FB_DIV);  in radeon_pm_save_regs()
666 	rinfo->save_regs[78] = INPLL(pllAGP_PLL_CNTL);  in radeon_pm_save_regs()
677 	rinfo->save_regs[89] = INPLL(pllP2PLL_REF_DIV);  in radeon_pm_save_regs()
678 	rinfo->save_regs[92] = INPLL(pllPPLL_DIV_0);  in radeon_pm_save_regs()
679 	rinfo->save_regs[93] = INPLL(pllPPLL_CNTL);  in radeon_pm_save_regs()
683 	rinfo->save_regs[97] = INPLL(pllMDLL_CKO);  in radeon_pm_save_regs()
684 	rinfo->save_regs[98] = INPLL(pllMDLL_RDCKA);  in radeon_pm_save_regs()
685 	rinfo->save_regs[99] = INPLL(pllMDLL_RDCKB);  in radeon_pm_save_regs()
760 		INPLL(pllP2PLL_REF_DIV);  in radeon_pm_program_v2clk()
766 	OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_SLEEP);  in radeon_pm_program_v2clk()
769 	OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_RESET);  in radeon_pm_program_v2clk()
773   		(INPLL(pllPIXCLKS_CNTL) & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK)  in radeon_pm_program_v2clk()
791 	reg  = INPLL(PLL_PWRMGT_CNTL);  in radeon_pm_low_current()
837 	sclk_cntl = INPLL( pllSCLK_CNTL);  in radeon_pm_setup_for_suspend()
874 	sclk_more_cntl = INPLL(pllSCLK_MORE_CNTL);  in radeon_pm_setup_for_suspend()
882 	mclk_cntl = INPLL( pllMCLK_CNTL);  in radeon_pm_setup_for_suspend()
892 	vclk_ecp_cntl = INPLL( pllVCLK_ECP_CNTL);  in radeon_pm_setup_for_suspend()
899 	pixclks_cntl = INPLL( pllPIXCLKS_CNTL);  in radeon_pm_setup_for_suspend()
915 	pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL);  in radeon_pm_setup_for_suspend()
925 	clk_pwrmgt_cntl	 = INPLL( pllCLK_PWRMGT_CNTL);  in radeon_pm_setup_for_suspend()
947 	clk_pin_cntl = INPLL( pllCLK_PIN_CNTL);  in radeon_pm_setup_for_suspend()
952 	tmp = INPLL( pllMCLK_MISC) | MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND;  in radeon_pm_setup_for_suspend()
989 	tmp = INPLL( pllPLL_PWRMGT_CNTL) & ~PLL_PWRMGT_CNTL__PM_MODE_SEL;  in radeon_pm_setup_for_suspend()
1032 	clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL);  in radeon_pm_setup_for_suspend()
1033 	pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL) ;  in radeon_pm_setup_for_suspend()
1034 	clk_pin_cntl 	= INPLL( pllCLK_PIN_CNTL);  in radeon_pm_setup_for_suspend()
1152 	u32 cko = INPLL(pllMDLL_CKO)   | MDLL_CKO__MCKOA_SLEEP  in radeon_pm_enable_dll()
1154 	u32 cka = INPLL(pllMDLL_RDCKA) | MDLL_RDCKA__MRDCKA0_SLEEP  in radeon_pm_enable_dll()
1157 	u32 ckb = INPLL(pllMDLL_RDCKB) | MDLL_RDCKB__MRDCKB0_SLEEP  in radeon_pm_enable_dll()
1232 	dll_value = INPLL(pllMDLL_RDCKA);  in radeon_pm_enable_dll_m10()
1465 	tmp = INPLL(pllPPLL_CNTL);  in radeon_pm_all_ppls_off()
1467 	tmp = INPLL(pllP2PLL_CNTL);  in radeon_pm_all_ppls_off()
1469 	tmp = INPLL(pllSPLL_CNTL);  in radeon_pm_all_ppls_off()
1471 	tmp = INPLL(pllMPLL_CNTL);  in radeon_pm_all_ppls_off()
1480 	tmp = INPLL(pllSCLK_CNTL);  in radeon_pm_start_mclk_sclk()
1484 	tmp = INPLL(pllSPLL_CNTL);  in radeon_pm_start_mclk_sclk()
1491 	tmp = INPLL(pllM_SPLL_REF_FB_DIV);  in radeon_pm_start_mclk_sclk()
1496 	tmp = INPLL(pllSPLL_CNTL);  in radeon_pm_start_mclk_sclk()
1498 	(void)INPLL(pllSPLL_CNTL);  in radeon_pm_start_mclk_sclk()
1503 	tmp = INPLL(pllSPLL_CNTL);  in radeon_pm_start_mclk_sclk()
1505 	(void)INPLL(pllSPLL_CNTL);  in radeon_pm_start_mclk_sclk()
1510 	tmp = INPLL(pllSCLK_CNTL);  in radeon_pm_start_mclk_sclk()
1514 	(void)INPLL(pllSCLK_CNTL);  in radeon_pm_start_mclk_sclk()
1519 	tmp = INPLL(pllMPLL_CNTL);  in radeon_pm_start_mclk_sclk()
1526 	tmp = INPLL(pllM_SPLL_REF_FB_DIV);  in radeon_pm_start_mclk_sclk()
1531 	tmp = INPLL(pllMPLL_CNTL);  in radeon_pm_start_mclk_sclk()
1533 	(void)INPLL(pllMPLL_CNTL);  in radeon_pm_start_mclk_sclk()
1538 	tmp = INPLL(pllMPLL_CNTL);  in radeon_pm_start_mclk_sclk()
1540 	(void)INPLL(pllMPLL_CNTL);  in radeon_pm_start_mclk_sclk()
1545 	tmp = INPLL(pllMCLK_CNTL);  in radeon_pm_start_mclk_sclk()
1548 	(void)INPLL(pllMCLK_CNTL);  in radeon_pm_start_mclk_sclk()
1600 	tmp = INPLL(pllSSPLL_CNTL);  in radeon_pm_m10_enable_lvds_spread_spectrum()
1603 	tmp = INPLL(pllSSPLL_CNTL);  in radeon_pm_m10_enable_lvds_spread_spectrum()
1632 	tmp = INPLL(pllSS_TST_CNTL);  in radeon_pm_m10_enable_lvds_spread_spectrum()
1646 	tmp = INPLL(pllVCLK_ECP_CNTL);  in radeon_pm_restore_pixel_pll()
1650 	tmp = INPLL(pllPPLL_REF_DIV);  in radeon_pm_restore_pixel_pll()
1653 	INPLL(pllPPLL_REF_DIV);  in radeon_pm_restore_pixel_pll()
1658 	tmp = INPLL(pllPPLL_CNTL);  in radeon_pm_restore_pixel_pll()
1669 	tmp = INPLL(pllPPLL_CNTL);  in radeon_pm_restore_pixel_pll()
1673 	tmp = INPLL(pllPPLL_CNTL);  in radeon_pm_restore_pixel_pll()
1677 	tmp = INPLL(pllVCLK_ECP_CNTL);  in radeon_pm_restore_pixel_pll()
1681 	tmp = INPLL(pllVCLK_ECP_CNTL);  in radeon_pm_restore_pixel_pll()
1816 	tmp = INPLL(pllSCLK_CNTL);  in radeon_reinitialize_M10()
1883 	tmp = INPLL(pllSCLK_CNTL2); /* What for ? */  in radeon_reinitialize_M10()
1886 	tmp = INPLL(pllSCLK_MORE_CNTL);  in radeon_reinitialize_M10()
2158 	tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff;  in radeon_reinitialize_M9P()
2163 	tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff;  in radeon_reinitialize_M9P()
2181 	tmp = INPLL(pllSSPLL_CNTL);  in radeon_reinitialize_M9P()
2256 	tmp = INPLL(pllVCLK_ECP_CNTL);
2258 	tmp = INPLL(pllPIXCLKS_CNTL);
2273 	tmp = INPLL(M_SPLL_REF_FB_DIV);
2275 	tmp = INPLL(M_SPLL_REF_FB_DIV);
2277 	INPLL(M_SPLL_REF_FB_DIV);
2279 	tmp = INPLL(MPLL_CNTL);
2285 	tmp = INPLL(M_SPLL_REF_FB_DIV);
2288 	tmp = INPLL(MPLL_CNTL);
2291 	tmp = INPLL(MPLL_CNTL);
2298 	INPLL(M_SPLL_REF_FB_DIV);
2299 	INPLL(MCLK_CNTL);
2300 	INPLL(M_SPLL_REF_FB_DIV);
2302 	tmp = INPLL(SPLL_CNTL);
2308 	tmp = INPLL(M_SPLL_REF_FB_DIV);
2311 	tmp = INPLL(SPLL_CNTL);
2314 	tmp = INPLL(SPLL_CNTL);
2318 	tmp = INPLL(SCLK_CNTL);
2322 	cko = INPLL(pllMDLL_CKO);
2323 	cka = INPLL(pllMDLL_RDCKA);
2324 	ckb = INPLL(pllMDLL_RDCKB);
2393 	tmp = INPLL(MCLK_MISC);
2397 	tmp = INPLL(SCLK_CNTL);
2405 	tmp = INPLL(VCLK_ECP_CNTL);
2408 	tmp = INPLL(PPLL_CNTL);
2452 	tmp = INPLL(PPLL_REF_DIV);
2455 	INPLL(PPLL_REF_DIV);
2470 	tmp = INPLL(PPLL_CNTL);
2473 	tmp = INPLL(PPLL_CNTL);
2477 	tmp = INPLL(VCLK_ECP_CNTL);
2481 	tmp = INPLL(VCLK_ECP_CNTL);
2582 				tmp = INPLL( pllMDLL_CKO) | MDLL_CKO__MCKOA_RESET  in radeon_set_suspend()
2712 	return rinfo->save_regs[4] != INPLL(CLK_PIN_CNTL) ||  in radeon_check_power_loss()
2713 	       rinfo->save_regs[2] != INPLL(MCLK_CNTL) ||  in radeon_check_power_loss()
2714 	       rinfo->save_regs[3] != INPLL(SCLK_CNTL);  in radeon_check_power_loss()