Lines Matching refs:U3D_EP0CSR
142 csr = mtu3_readl(mbase, U3D_EP0CSR) & EP0_W1C_BITS; in ep0_stall_set()
147 mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr); in ep0_stall_set()
300 value = mtu3_readl(mbase, U3D_EP0CSR) & EP0_W1C_BITS; in handle_test_mode()
301 mtu3_writel(mbase, U3D_EP0CSR, value | EP0_SETUPPKTRDY | EP0_DATAEND); in handle_test_mode()
304 readl_poll_timeout_atomic(mbase + U3D_EP0CSR, value, in handle_test_mode()
512 csr = mtu3_readl(mbase, U3D_EP0CSR) & EP0_W1C_BITS; in ep0_rx_state()
546 mtu3_writel(mbase, U3D_EP0CSR, csr); in ep0_rx_state()
588 csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR) & EP0_W1C_BITS; in ep0_tx_state()
589 mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr | EP0_TXPKTRDY); in ep0_tx_state()
592 mtu3_readl(mtu->mac_base, U3D_EP0CSR)); in ep0_tx_state()
601 csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR) & EP0_W1C_BITS; in ep0_read_setup()
619 mtu3_writel(mtu->mac_base, U3D_EP0CSR, in ep0_read_setup()
623 mtu3_writel(mtu->mac_base, U3D_EP0CSR, in ep0_read_setup()
671 mtu3_writel(mbase, U3D_EP0CSR, in ep0_handle_setup()
672 (mtu3_readl(mbase, U3D_EP0CSR) & EP0_W1C_BITS) in ep0_handle_setup()
705 csr = mtu3_readl(mbase, U3D_EP0CSR); in mtu3_ep0_isr()
712 csr = mtu3_readl(mbase, U3D_EP0CSR); in mtu3_ep0_isr()
734 mtu3_writel(mbase, U3D_EP0CSR, in mtu3_ep0_isr()
808 csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR) & EP0_W1C_BITS; in ep0_queue()
810 mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr); in ep0_queue()