272 		ir = &xhci->run_regs->ir_set[i];  in xhci_zero_64b_regs()
655 	temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);  in xhci_run()
662 	temp = readl(&xhci->ir_set->irq_control);  in xhci_run()
665 	writel(temp, &xhci->ir_set->irq_control);  in xhci_run()
674 	temp = readl(&xhci->ir_set->irq_pending);  in xhci_run()
677 			xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));  in xhci_run()
678 	writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);  in xhci_run()
752 	temp = readl(&xhci->ir_set->irq_pending);  in xhci_stop()
753 	writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);  in xhci_stop()
805 	xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);  in xhci_save_registers()
806 	xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);  in xhci_save_registers()
807 	xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);  in xhci_save_registers()
808 	xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);  in xhci_save_registers()
809 	xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);  in xhci_save_registers()
818 	writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);  in xhci_restore_registers()
819 	xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);  in xhci_restore_registers()
820 	xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);  in xhci_restore_registers()
821 	writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);  in xhci_restore_registers()
822 	writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);  in xhci_restore_registers()
1170 		temp = readl(&xhci->ir_set->irq_pending);  in xhci_resume()
1171 		writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);  in xhci_resume()