195 	hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));  in hw_port_test_set()
229 		hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),  in ci_hdrc_enter_lpm()
232 		hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),  in ci_hdrc_enter_lpm()
267 	hw_write(ci, OP_USBINTR, 0xffffffff, 0);  in hw_device_init()
270 	hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);  in hw_device_init()
318 		hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);  in hw_phymode_configure()
320 			hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);  in hw_phymode_configure()
322 		hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);  in hw_phymode_configure()
324 			hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);  in hw_phymode_configure()
432 			hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,  in ci_platform_configure()
440 			hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,  in ci_platform_configure()
446 			hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);  in ci_platform_configure()
448 			hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);  in ci_platform_configure()
452 		hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);  in ci_platform_configure()
454 	hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16);  in ci_platform_configure()
463 			hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,  in ci_platform_configure()
467 			hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,  in ci_platform_configure()
482 	hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);  in hw_controller_reset()
503 	hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);  in hw_device_reset()
504 	hw_write(ci, OP_USBCMD, USBCMD_RS, 0);  in hw_device_reset()
520 	hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);  in hw_device_reset()
521 	hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);  in hw_device_reset()
523 	hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);  in hw_device_reset()
1230 		hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,  in ci_otg_fsm_suspend_for_srp()
1232 		hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,  in ci_otg_fsm_suspend_for_srp()