1498 	unsigned char RegValue;  in set_break()  local
1510 	RegValue = read_reg(info, CTL);  in set_break()
1512 		RegValue |= BIT3;  in set_break()
1514 		RegValue &= ~BIT3;  in set_break()
1515 	write_reg(info, CTL, RegValue);  in set_break()
4364   	unsigned char RegValue;  in async_mode()  local
4379 	RegValue = 0x00;  in async_mode()
4381 		RegValue |= BIT1;  in async_mode()
4382 	write_reg(info, MD0, RegValue);  in async_mode()
4393 	RegValue = 0x40;  in async_mode()
4395 	case 7: RegValue |= BIT4 + BIT2; break;  in async_mode()
4396 	case 6: RegValue |= BIT5 + BIT3; break;  in async_mode()
4397 	case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;  in async_mode()
4400 		RegValue |= BIT1;  in async_mode()
4402 			RegValue |= BIT0;  in async_mode()
4404 	write_reg(info, MD1, RegValue);  in async_mode()
4413 	RegValue = 0x00;  in async_mode()
4415 		RegValue |= (BIT1 + BIT0);  in async_mode()
4416 	write_reg(info, MD2, RegValue);  in async_mode()
4424 	RegValue=BIT6;  in async_mode()
4425 	write_reg(info, RXS, RegValue);  in async_mode()
4433 	RegValue=BIT6;  in async_mode()
4434 	write_reg(info, TXS, RegValue);  in async_mode()
4478 	RegValue = 0x10;  in async_mode()
4480 		RegValue |= 0x01;  in async_mode()
4481 	write_reg(info, CTL, RegValue);  in async_mode()
4502 	unsigned char RegValue;  in hdlc_mode()  local
4526 	RegValue = 0x81;  in hdlc_mode()
4528 		RegValue |= BIT4;  in hdlc_mode()
4530 		RegValue |= BIT4;  in hdlc_mode()
4532 		RegValue |= BIT2 + BIT1;  in hdlc_mode()
4533 	write_reg(info, MD0, RegValue);  in hdlc_mode()
4544 	RegValue = 0x00;  in hdlc_mode()
4545 	write_reg(info, MD1, RegValue);  in hdlc_mode()
4557 	RegValue = 0x00;  in hdlc_mode()
4559 	case HDLC_ENCODING_NRZI:	  RegValue |= BIT5; break;  in hdlc_mode()
4560 	case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */  in hdlc_mode()
4561 	case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */  in hdlc_mode()
4562 	case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; 	/* aka Manchester */  in hdlc_mode()
4571 		RegValue |= BIT3;  in hdlc_mode()
4576 		RegValue |= BIT4;  in hdlc_mode()
4578 	write_reg(info, MD2, RegValue);  in hdlc_mode()
4587 	RegValue=0;  in hdlc_mode()
4589 		RegValue |= BIT6;  in hdlc_mode()
4591 		RegValue |= BIT6 + BIT5;  in hdlc_mode()
4592 	write_reg(info, RXS, RegValue);  in hdlc_mode()
4600 	RegValue=0;  in hdlc_mode()
4602 		RegValue |= BIT6;  in hdlc_mode()
4604 		RegValue |= BIT6 + BIT5;  in hdlc_mode()
4605 	write_reg(info, TXS, RegValue);  in hdlc_mode()
4683 	RegValue = 0x10;  in hdlc_mode()
4685 		RegValue |= 0x01;  in hdlc_mode()
4686 	write_reg(info, CTL, RegValue);  in hdlc_mode()
4704 	unsigned char RegValue = 0xff;  in tx_set_idle()  local
4708 	case HDLC_TXIDLE_FLAGS:			RegValue = 0x7e; break;  in tx_set_idle()
4709 	case HDLC_TXIDLE_ALT_ZEROS_ONES:	RegValue = 0xaa; break;  in tx_set_idle()
4710 	case HDLC_TXIDLE_ZEROS:			RegValue = 0x00; break;  in tx_set_idle()
4711 	case HDLC_TXIDLE_ONES:			RegValue = 0xff; break;  in tx_set_idle()
4712 	case HDLC_TXIDLE_ALT_MARK_SPACE:	RegValue = 0xaa; break;  in tx_set_idle()
4713 	case HDLC_TXIDLE_SPACE:			RegValue = 0x00; break;  in tx_set_idle()
4714 	case HDLC_TXIDLE_MARK:			RegValue = 0xff; break;  in tx_set_idle()
4717 	write_reg(info, IDL, RegValue);  in tx_set_idle()
4753 	unsigned char RegValue;  in set_signals()  local
4756 	RegValue = read_reg(info, CTL);  in set_signals()
4758 		RegValue &= ~BIT0;  in set_signals()
4760 		RegValue |= BIT0;  in set_signals()
4761 	write_reg(info, CTL, RegValue);  in set_signals()