Lines Matching refs:TCR
394 #define TCR 0x82 /* tx control */ macro
1385 value = rd_reg16(info, TCR); in set_break()
1390 wr_reg16(info, TCR, value); in set_break()
2268 unsigned short val = rd_reg16(info, TCR); in isr_txeom()
2269 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ in isr_txeom()
2270 wr_reg16(info, TCR, val); /* clear reset bit */ in isr_txeom()
2853 val = rd_reg16(info, TCR); in set_interface()
2858 wr_reg16(info, TCR, val); in set_interface()
4010 wr_reg16(info, TCR, in tx_start()
4011 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2)); in tx_start()
4054 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */ in tx_stop()
4055 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ in tx_stop()
4141 wr_reg16(info, TCR, val); in async_mode()
4303 wr_reg16(info, TCR, val); in sync_mode()
4465 tcr = rd_reg16(info, TCR); in tx_set_idle()
4475 wr_reg16(info, TCR, tcr); in tx_set_idle()
4964 wr_reg16(info, TCR, in irq_test()
4965 (unsigned short)(rd_reg16(info, TCR) | BIT1)); in irq_test()