Lines Matching refs:usc_InReg
607 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
610 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
613 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
616 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
645 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
648 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
660 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
662 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
668 static u16 usc_InReg( struct mgsl_struct *info, u16 Port );
1161 u16 status = usc_InReg( info, RCSR ); in mgsl_isr_receive_status()
1180 (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED)); in mgsl_isr_receive_status()
1213 u16 status = usc_InReg( info, TCSR ); in mgsl_isr_transmit_status()
1281 u16 status = usc_InReg( info, MISR ); in mgsl_isr_io_pin()
1385 (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) ); in mgsl_isr_io_pin()
1450 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 )); in mgsl_isr_receive_data()
1454 while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) { in mgsl_isr_receive_data()
1463 status = usc_InReg(info, RCSR); in mgsl_isr_receive_data()
1533 u16 status = usc_InReg( info, MISR ); in mgsl_isr_misc()
1692 UscVector = usc_InReg(info, IVR) >> 9; in mgsl_interrupt()
1839 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14)); in shutdown()
1844 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12)); in shutdown()
2696 u16 oldreg = usc_InReg(info,RICR); in mgsl_wait_event()
2764 usc_OutReg(info, RICR, usc_InReg(info,RICR) & in mgsl_wait_event()
2900 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7)); in mgsl_break()
2902 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7)); in mgsl_break()
3155 while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) && in mgsl_wait_until_sent()
3503 u16 Tcsr = usc_InReg( info, TCSR ); in line_info()
3505 u16 Ticr = usc_InReg( info, TICR ); in line_info()
3506 u16 Rscr = usc_InReg( info, RCSR ); in line_info()
3508 u16 Ricr = usc_InReg( info, RICR ); in line_info()
3509 u16 Icr = usc_InReg( info, ICR ); in line_info()
3510 u16 Dccr = usc_InReg( info, DCCR ); in line_info()
3511 u16 Tmr = usc_InReg( info, TMR ); in line_info()
3512 u16 Tccr = usc_InReg( info, TCCR ); in line_info()
4550 static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr ) in usc_InReg() function
4579 RegValue=usc_InReg(info,TMDR); in usc_set_sdlc_mode()
4620 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12)); in usc_set_sdlc_mode()
4729 RegValue = usc_InReg( info, RICR ) & 0xc0; in usc_set_sdlc_mode()
4972 (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) ); in usc_set_sdlc_mode()
4983 usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3)); in usc_set_sdlc_mode()
5138 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7 | BIT6)); in usc_enable_loopback()
5167 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_loopback()
5170 usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004)); in usc_enable_loopback()
5177 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7 | BIT6)); in usc_enable_loopback()
5230 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_aux_clock()
5233 usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) ); in usc_enable_aux_clock()
5236 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) ); in usc_enable_aux_clock()
5356 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) ); in usc_process_rxoverrun_sync()
5381 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) ); in usc_process_rxoverrun_sync()
5411 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) ); in usc_stop_receiver()
5438 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) ); in usc_start_receiver()
5639 while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) { in usc_load_txfifo()
6040 if (usc_InReg( info, RCSR ) & (BIT8 | BIT4 | BIT3 | BIT1)) in usc_loopback_frame()
6147 status = usc_InReg( info, MISR ); in usc_get_serial_signals()
6180 Control = usc_InReg( info, PCR ); in usc_set_serial_signals()
6244 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_async_clock()
6250 (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) ); in usc_enable_async_clock()
6253 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) ); in usc_enable_async_clock()
6881 if ( (usc_InReg( info, SICR ) != 0) || in mgsl_register_test()
6882 (usc_InReg( info, IVR ) != 0) || in mgsl_register_test()
6899 if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) || in mgsl_register_test()
6900 (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) || in mgsl_register_test()
6901 (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) || in mgsl_register_test()
6902 (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) || in mgsl_register_test()
6903 (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) || in mgsl_register_test()
6942 usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) ); in mgsl_irq_test()
7081 usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) ); in mgsl_dma_test()
7132 usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) ); in mgsl_dma_test()
7156 FifoLevel = usc_InReg(info, TICR) >> 8; in mgsl_dma_test()
7179 usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) ); in mgsl_dma_test()
7194 status = usc_InReg( info, TCSR ); in mgsl_dma_test()
7204 status = usc_InReg( info, TCSR ); in mgsl_dma_test()
7536 (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) ); in usc_loopmode_insert_request()
7547 return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ; in usc_loopmode_active()