Lines Matching refs:RICR
357 #define RICR 0x26 /* Receive Interrupt Control Register */ macro
1179 usc_OutReg(info, RICR, in mgsl_isr_receive_status()
1180 (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED)); in mgsl_isr_receive_status()
1450 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 )); in mgsl_isr_receive_data()
1454 while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) { in mgsl_isr_receive_data()
2696 u16 oldreg = usc_InReg(info,RICR); in mgsl_wait_event()
2701 usc_OutReg(info, RICR, newreg); in mgsl_wait_event()
2764 usc_OutReg(info, RICR, usc_InReg(info,RICR) & in mgsl_wait_event()
3508 u16 Ricr = usc_InReg( info, RICR ); in line_info()
4729 RegValue = usc_InReg( info, RICR ) & 0xc0; in usc_set_sdlc_mode()
4732 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) ); in usc_set_sdlc_mode()
4734 usc_OutReg( info, RICR, (u16)(0x140a | RegValue) ); in usc_set_sdlc_mode()
5878 usc_OutReg( info, RICR, 0x0000 ); in usc_set_async_mode()
7535 usc_OutReg( info, RICR, in usc_loopmode_insert_request()
7536 (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) ); in usc_loopmode_insert_request()