Lines Matching refs:rd_regl
72 reg = rd_regl(port, ureg->sirfsoc_tx_fifo_status); in sirfsoc_uart_tx_empty()
83 if (!(rd_regl(port, ureg->sirfsoc_afc_ctrl) & in sirfsoc_uart_get_mctrl()
111 rd_regl(port, ureg->sirfsoc_line_ctrl) | in sirfsoc_uart_set_mctrl()
115 rd_regl(port, ureg->sirfsoc_mode1) | in sirfsoc_uart_set_mctrl()
120 rd_regl(port, ureg->sirfsoc_line_ctrl) & in sirfsoc_uart_set_mctrl()
124 rd_regl(port, ureg->sirfsoc_mode1) & in sirfsoc_uart_set_mctrl()
131 current_val = rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0xFF; in sirfsoc_uart_set_mctrl()
155 rd_regl(port, ureg->sirfsoc_int_en_reg) & in sirfsoc_uart_stop_tx()
163 wr_regl(port, ureg->sirfsoc_tx_rx_en, rd_regl(port, in sirfsoc_uart_stop_tx()
167 rd_regl(port, ureg->sirfsoc_int_en_reg) & in sirfsoc_uart_stop_tx()
198 rd_regl(port, ureg->sirfsoc_int_en_reg)& in sirfsoc_uart_tx_with_dma()
214 rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)| in sirfsoc_uart_tx_with_dma()
225 rd_regl(port, ureg->sirfsoc_int_en_reg)| in sirfsoc_uart_tx_with_dma()
235 rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)& in sirfsoc_uart_tx_with_dma()
270 wr_regl(port, ureg->sirfsoc_tx_rx_en, rd_regl(port, in sirfsoc_uart_start_tx()
277 rd_regl(port, ureg->sirfsoc_int_en_reg)| in sirfsoc_uart_start_tx()
295 rd_regl(port, ureg->sirfsoc_int_en_reg) & in sirfsoc_uart_stop_rx()
308 rd_regl(port, ureg->sirfsoc_int_en_reg)& in sirfsoc_uart_stop_rx()
329 rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0x3FF); in sirfsoc_uart_disable_ms()
332 rd_regl(port, ureg->sirfsoc_int_en_reg)& in sirfsoc_uart_disable_ms()
364 rd_regl(port, ureg->sirfsoc_afc_ctrl) | in sirfsoc_uart_enable_ms()
369 rd_regl(port, ureg->sirfsoc_int_en_reg) in sirfsoc_uart_enable_ms()
383 unsigned long ulcon = rd_regl(port, ureg->sirfsoc_line_ctrl); in sirfsoc_uart_break_ctl()
403 while (!(rd_regl(port, ureg->sirfsoc_rx_fifo_status) & in sirfsoc_uart_pio_rx_chars()
405 ch = rd_regl(port, ureg->sirfsoc_rx_fifo_data) | in sirfsoc_uart_pio_rx_chars()
429 !(rd_regl(port, ureg->sirfsoc_tx_fifo_status) & in sirfsoc_uart_pio_tx_chars()
478 intr_status = rd_regl(port, ureg->sirfsoc_int_st_reg); in sirfsoc_uart_isr()
480 intr_status &= rd_regl(port, ureg->sirfsoc_int_en_reg); in sirfsoc_uart_isr()
511 cts_status = rd_regl(port, ureg->sirfsoc_afc_ctrl) & in sirfsoc_uart_isr()
535 rd_regl(port, ureg->sirfsoc_int_en_reg) in sirfsoc_uart_isr()
538 rd_regl(port, ureg->sirfsoc_int_en_reg) in sirfsoc_uart_isr()
550 rd_regl(port, ureg->sirfsoc_int_en_reg) in sirfsoc_uart_isr()
553 rd_regl(port, ureg->sirfsoc_int_en_reg) in sirfsoc_uart_isr()
580 (rd_regl(port, ureg->sirfsoc_tx_fifo_status) & in sirfsoc_uart_isr()
602 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) & in sirfsoc_uart_start_next_rx_dma()
623 rd_regl(port, ureg->sirfsoc_int_en_reg) | in sirfsoc_uart_start_next_rx_dma()
824 txfifo_op_reg = rd_regl(port, ureg->sirfsoc_tx_fifo_op); in sirfsoc_uart_set_termios()
861 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) & in sirfsoc_uart_set_termios()
865 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) | in sirfsoc_uart_set_termios()
914 rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl) | in sirfsoc_uart_startup()
917 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) | in sirfsoc_uart_startup()
920 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) & in sirfsoc_uart_startup()
966 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) | in sirfsoc_uart_startup()
985 rd_regl(port, ureg->sirfsoc_int_en_reg) | in sirfsoc_uart_startup()
1025 while (((rd_regl(port, ureg->sirfsoc_rx_fifo_status) & in sirfsoc_uart_shutdown()
1120 while (rd_regl(port, ureg->sirfsoc_tx_fifo_status) & in sirfsoc_uart_console_putchar()
1216 ((rd_regl(port, ureg->sirfsoc_rx_fifo_status) & in sirfsoc_uart_rx_dma_hrtimer_callback()
1221 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) | in sirfsoc_uart_rx_dma_hrtimer_callback()
1236 while (!(rd_regl(port, ureg->sirfsoc_rx_fifo_status) & in sirfsoc_uart_rx_dma_hrtimer_callback()
1239 rd_regl(port, ureg->sirfsoc_rx_fifo_data); in sirfsoc_uart_rx_dma_hrtimer_callback()
1246 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) & in sirfsoc_uart_rx_dma_hrtimer_callback()