Lines Matching full:fifo
34 #define ATMEL_US_TXFCLR BIT(24) /* Transmit FIFO Clear */
35 #define ATMEL_US_RXFCLR BIT(25) /* Receive FIFO Clear */
36 #define ATMEL_US_TXFLCLR BIT(26) /* Transmit FIFO Lock Clear */
37 #define ATMEL_US_FIFOEN BIT(30) /* FIFO enable */
38 #define ATMEL_US_FIFODIS BIT(31) /* FIFO disable */
133 #define ATMEL_US_FMR 0xa0 /* FIFO Mode Register */
139 #define ATMEL_US_FRTSC BIT(7) /* FIFO RTS pin Control */
140 #define ATMEL_US_TXFTHRES(thr) (((thr) & 0x3f) << 8) /* TX FIFO Threshold */
141 #define ATMEL_US_RXFTHRES(thr) (((thr) & 0x3f) << 16) /* RX FIFO Threshold */
142 #define ATMEL_US_RXFTHRES2(thr) (((thr) & 0x3f) << 24) /* RX FIFO Threshold2 */
144 #define ATMEL_US_FLR 0xa4 /* FIFO Level Register */
145 #define ATMEL_US_TXFL(reg) (((reg) >> 0) & 0x3f) /* TX FIFO Level */
146 #define ATMEL_US_RXFL(reg) (((reg) >> 16) & 0x3f) /* RX FIFO Level */
148 #define ATMEL_US_FIER 0xa8 /* FIFO Interrupt Enable Register */
149 #define ATMEL_US_FIDR 0xac /* FIFO Interrupt Disable Register */
150 #define ATMEL_US_FIMR 0xb0 /* FIFO Interrupt Mask Register */
151 #define ATMEL_US_FESR 0xb4 /* FIFO Event Status Register */
152 #define ATMEL_US_TXFEF BIT(0) /* Transmit FIFO Empty Flag */
153 #define ATMEL_US_TXFFF BIT(1) /* Transmit FIFO Full Flag */
154 #define ATMEL_US_TXFTHF BIT(2) /* Transmit FIFO Threshold Flag */
155 #define ATMEL_US_RXFEF BIT(3) /* Receive FIFO Empty Flag */
156 #define ATMEL_US_RXFFF BIT(4) /* Receive FIFO Full Flag */
157 #define ATMEL_US_RXFTHF BIT(5) /* Receive FIFO Threshold Flag */
158 #define ATMEL_US_TXFPTEF BIT(6) /* Transmit FIFO Pointer Error Flag */
159 #define ATMEL_US_RXFPTEF BIT(7) /* Receive FIFO Pointer Error Flag */
160 #define ATMEL_US_TXFLOCK BIT(8) /* Transmit FIFO Lock (FESR only) */
161 #define ATMEL_US_RXFTHF2 BIT(9) /* Receive FIFO Threshold Flag 2 */