298 static void pl011_write(unsigned int val, const struct uart_amba_port *uap,  in pl011_write()  function
562 	pl011_write(uap->dmacr, uap, REG_DMACR);  in pl011_dma_tx_callback()
676 	pl011_write(uap->dmacr, uap, REG_DMACR);  in pl011_dma_tx_refill()
712 		pl011_write(uap->dmacr, uap, REG_DMACR);  in pl011_dma_tx_irq()
714 		pl011_write(uap->im, uap, REG_IMSC);  in pl011_dma_tx_irq()
724 		pl011_write(uap->im, uap, REG_IMSC);  in pl011_dma_tx_irq()
738 		pl011_write(uap->dmacr, uap, REG_DMACR);  in pl011_dma_tx_stop()
764 				pl011_write(uap->im, uap, REG_IMSC);  in pl011_dma_tx_start()
769 			pl011_write(uap->dmacr, uap, REG_DMACR);  in pl011_dma_tx_start()
780 	pl011_write(uap->dmacr, uap, REG_DMACR);  in pl011_dma_tx_start()
791 	pl011_write(uap->port.x_char, uap, REG_DR);  in pl011_dma_tx_start()
797 	pl011_write(dmacr, uap, REG_DMACR);  in pl011_dma_tx_start()
825 		pl011_write(uap->dmacr, uap, REG_DMACR);  in pl011_dma_flush_buffer()
865 	pl011_write(uap->dmacr, uap, REG_DMACR);  in pl011_dma_rx_trigger_dma()
869 	pl011_write(uap->im, uap, REG_IMSC);  in pl011_dma_rx_trigger_dma()
927 		pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |  in pl011_dma_rx_chars()
976 	pl011_write(uap->dmacr, uap, REG_DMACR);  in pl011_dma_rx_irq()
996 		pl011_write(uap->im, uap, REG_IMSC);  in pl011_dma_rx_irq()
1044 		pl011_write(uap->im, uap, REG_IMSC);  in pl011_dma_rx_callback()
1057 	pl011_write(uap->dmacr, uap, REG_DMACR);  in pl011_dma_rx_stop()
1101 		pl011_write(uap->im, uap, REG_IMSC);  in pl011_dma_rx_poll()
1163 	pl011_write(uap->dmacr, uap, REG_DMACR);  in pl011_dma_startup()
1171 		pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,  in pl011_dma_startup()
1200 	pl011_write(uap->dmacr, uap, REG_DMACR);  in pl011_dma_shutdown()
1301 	pl011_write(uap->im, uap, REG_IMSC);  in pl011_stop_tx()
1312 		pl011_write(uap->im, uap, REG_IMSC);  in pl011_start_tx_pio()
1332 	pl011_write(uap->im, uap, REG_IMSC);  in pl011_stop_rx()
1343 	pl011_write(uap->im, uap, REG_IMSC);  in pl011_enable_ms()
1363 			pl011_write(uap->im, uap, REG_IMSC);  in pl011_rx_chars()
1387 	pl011_write(c, uap, REG_DR);  in pl011_tx_char()
1467 	pl011_write(0x00, uap, REG_ICR);  in check_apply_cts_event_workaround()
1491 			pl011_write(status & ~(UART011_TXIS|UART011_RTIS|  in pl011_int()
1577 	pl011_write(cr, uap, REG_CR);  in pl011_set_mctrl()
1593 	pl011_write(lcr_h, uap, REG_LCRH_TX);  in pl011_break_ctl()
1604 	pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);  in pl011_quiesce_irqs()
1618 	pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,  in pl011_quiesce_irqs()
1650 	pl011_write(ch, uap, REG_DR);  in pl011_put_poll_char()
1674 	pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |  in pl011_hwinit()
1683 	pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);  in pl011_hwinit()
1703 	pl011_write(lcr_h, uap, REG_LCRH_RX);  in pl011_write_lcr_h()
1711 			pl011_write(0xff, uap, REG_MIS);  in pl011_write_lcr_h()
1712 		pl011_write(lcr_h, uap, REG_LCRH_TX);  in pl011_write_lcr_h()
1718 	pl011_write(uap->im, uap, REG_IMSC);  in pl011_allocate_irq()
1735 	pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);  in pl011_enable_interrupts()
1753 	pl011_write(uap->im, uap, REG_IMSC);  in pl011_enable_interrupts()
1772 	pl011_write(uap->vendor->ifls, uap, REG_IFLS);  in pl011_startup()
1779 	pl011_write(cr, uap, REG_CR);  in pl011_startup()
1829       pl011_write(val, uap, lcrh);  in pl011_shutdown_channel()
1847 	pl011_write(cr, uap, REG_CR);  in pl011_disable_uart()
1864 	pl011_write(uap->im, uap, REG_IMSC);  in pl011_disable_interrupts()
1865 	pl011_write(0xffff, uap, REG_ICR);  in pl011_disable_interrupts()
2020 	pl011_write(0, uap, REG_CR);  in pl011_set_termios()
2053 	pl011_write(quot & 0x3f, uap, REG_FBRD);  in pl011_set_termios()
2054 	pl011_write(quot >> 6, uap, REG_IBRD);  in pl011_set_termios()
2063 	pl011_write(old_cr, uap, REG_CR);  in pl011_set_termios()
2206 	pl011_write(ch, uap, REG_DR);  in pl011_console_putchar()
2234 		pl011_write(new_cr, uap, REG_CR);  in pl011_console_write()
2248 		pl011_write(old_cr, uap, REG_CR);  in pl011_console_write()
2601 	pl011_write(0, uap, REG_IMSC);  in pl011_register_port()
2602 	pl011_write(0xffff, uap, REG_ICR);  in pl011_register_port()