650 	void __iomem *controller_base = mt->thermal_base + offset;  in mtk_thermal_init_bank()  local
658 	writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);  in mtk_thermal_init_bank()
666 			controller_base + TEMP_MONCTL2);  in mtk_thermal_init_bank()
670 	       controller_base + TEMP_AHBPOLL);  in mtk_thermal_init_bank()
673 	writel(0x0, controller_base + TEMP_MSRCTL0);  in mtk_thermal_init_bank()
676 	writel(0xffffffff, controller_base + TEMP_AHBTO);  in mtk_thermal_init_bank()
679 	writel(0x0, controller_base + TEMP_MONIDET0);  in mtk_thermal_init_bank()
680 	writel(0x0, controller_base + TEMP_MONIDET1);  in mtk_thermal_init_bank()
695 	writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);  in mtk_thermal_init_bank()
699 	       controller_base + TEMP_ADCMUXADDR);  in mtk_thermal_init_bank()
703 	       controller_base + TEMP_PNPMUXADDR);  in mtk_thermal_init_bank()
706 	writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);  in mtk_thermal_init_bank()
710 	       controller_base + TEMP_ADCENADDR);  in mtk_thermal_init_bank()
714 	       controller_base + TEMP_ADCVALIDADDR);  in mtk_thermal_init_bank()
718 	       controller_base + TEMP_ADCVOLTADDR);  in mtk_thermal_init_bank()
721 	writel(0x0, controller_base + TEMP_RDCTRL);  in mtk_thermal_init_bank()
725 	       controller_base + TEMP_ADCVALIDMASK);  in mtk_thermal_init_bank()
728 	writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);  in mtk_thermal_init_bank()
732 		controller_base + TEMP_ADCWRITECTRL);  in mtk_thermal_init_bank()
740 	       controller_base + TEMP_MONCTL0);  in mtk_thermal_init_bank()
744 	       controller_base + TEMP_ADCWRITECTRL);  in mtk_thermal_init_bank()