Lines Matching full:spi
3 // STMicroelectronics STM32 SPI Controller driver (master mode only)
19 #include <linux/spi/spi.h>
23 /* STM32F4 SPI registers */
72 /* STM32F4 SPI Baud Rate min/max divisor */
76 /* STM32H7 SPI registers */
153 /* STM32H7 SPI Master Baud Rate min/max divisor */
157 /* STM32H7 SPI Communication mode */
163 /* SPI Communication type */
179 * stm32_spi_reg - stm32 SPI register & bitfield desc
192 * en: enable register and SPI enable bit
193 * dma_rx_en: SPI DMA RX enable register end SPI DMA RX enable bit
194 * dma_tx_en: SPI DMA TX enable register end SPI DMA TX enable bit
199 * rx: SPI RX data register
200 * tx: SPI TX data register
222 * @config: routine to configure controller as SPI Master
235 * @irq_handler_event: Interrupt handler for SPI controller events
236 * @irq_handler_thread: thread of interrupt handler for SPI controller
244 int (*get_fifo_size)(struct stm32_spi *spi);
245 int (*get_bpw_mask)(struct stm32_spi *spi);
246 void (*disable)(struct stm32_spi *spi);
247 int (*config)(struct stm32_spi *spi);
248 void (*set_bpw)(struct stm32_spi *spi);
249 int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type);
250 void (*set_data_idleness)(struct stm32_spi *spi, u32 length);
251 int (*set_number_of_data)(struct stm32_spi *spi, u32 length);
252 void (*transfer_one_dma_start)(struct stm32_spi *spi);
255 int (*transfer_one_irq)(struct stm32_spi *spi);
264 * struct stm32_spi - private data of the SPI controller
269 * @clk: hw kernel clock feeding the SPI clock generator
270 * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
271 * @rst: SPI controller reset line
273 * @irq: SPI controller interrupt line
277 * @cur_bpw: number of bits in a single SPI data frame
279 * @cur_comm: SPI communication mode
288 * @phys_addr: SPI registers physical base address
335 /* SPI data transfer is enabled but spi_ker_ck is idle.
353 static inline void stm32_spi_set_bits(struct stm32_spi *spi, in stm32_spi_set_bits() argument
356 writel_relaxed(readl_relaxed(spi->base + offset) | bits, in stm32_spi_set_bits()
357 spi->base + offset); in stm32_spi_set_bits()
360 static inline void stm32_spi_clr_bits(struct stm32_spi *spi, in stm32_spi_clr_bits() argument
363 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits, in stm32_spi_clr_bits()
364 spi->base + offset); in stm32_spi_clr_bits()
369 * @spi: pointer to the spi controller data structure
371 static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi) in stm32h7_spi_get_fifo_size() argument
376 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_get_fifo_size()
378 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); in stm32h7_spi_get_fifo_size()
380 while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP) in stm32h7_spi_get_fifo_size()
381 writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_get_fifo_size()
383 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); in stm32h7_spi_get_fifo_size()
385 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_get_fifo_size()
387 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count); in stm32h7_spi_get_fifo_size()
394 * @spi: pointer to the spi controller data structure
396 static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi) in stm32f4_spi_get_bpw_mask() argument
398 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n"); in stm32f4_spi_get_bpw_mask()
404 * @spi: pointer to the spi controller data structure
406 static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi) in stm32h7_spi_get_bpw_mask() argument
411 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_get_bpw_mask()
417 stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE); in stm32h7_spi_get_bpw_mask()
419 cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1); in stm32h7_spi_get_bpw_mask()
424 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_get_bpw_mask()
426 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw); in stm32h7_spi_get_bpw_mask()
433 * @spi: pointer to the spi controller data structure
440 static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz, in stm32_spi_prepare_mbr() argument
445 div = DIV_ROUND_UP(spi->clk_rate, speed_hz); in stm32_spi_prepare_mbr()
448 * SPI framework set xfer->speed_hz to master->max_speed_hz if in stm32_spi_prepare_mbr()
463 spi->cur_speed = spi->clk_rate / (1 << mbrdiv); in stm32_spi_prepare_mbr()
470 * @spi: pointer to the spi controller data structure
472 static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi) in stm32h7_spi_prepare_fthlv() argument
477 half_fifo = (spi->fifo_size / 2); in stm32h7_spi_prepare_fthlv()
479 if (spi->cur_bpw <= 8) in stm32h7_spi_prepare_fthlv()
481 else if (spi->cur_bpw <= 16) in stm32h7_spi_prepare_fthlv()
487 if (spi->cur_bpw > 8) in stm32h7_spi_prepare_fthlv()
497 * @spi: pointer to the spi controller data structure
502 static void stm32f4_spi_write_tx(struct stm32_spi *spi) in stm32f4_spi_write_tx() argument
504 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) & in stm32f4_spi_write_tx()
506 u32 offs = spi->cur_xferlen - spi->tx_len; in stm32f4_spi_write_tx()
508 if (spi->cur_bpw == 16) { in stm32f4_spi_write_tx()
509 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); in stm32f4_spi_write_tx()
511 writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR); in stm32f4_spi_write_tx()
512 spi->tx_len -= sizeof(u16); in stm32f4_spi_write_tx()
514 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); in stm32f4_spi_write_tx()
516 writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR); in stm32f4_spi_write_tx()
517 spi->tx_len -= sizeof(u8); in stm32f4_spi_write_tx()
521 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); in stm32f4_spi_write_tx()
526 * @spi: pointer to the spi controller data structure
531 static void stm32h7_spi_write_txfifo(struct stm32_spi *spi) in stm32h7_spi_write_txfifo() argument
533 while ((spi->tx_len > 0) && in stm32h7_spi_write_txfifo()
534 (readl_relaxed(spi->base + STM32H7_SPI_SR) & in stm32h7_spi_write_txfifo()
536 u32 offs = spi->cur_xferlen - spi->tx_len; in stm32h7_spi_write_txfifo()
538 if (spi->tx_len >= sizeof(u32)) { in stm32h7_spi_write_txfifo()
539 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
541 writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
542 spi->tx_len -= sizeof(u32); in stm32h7_spi_write_txfifo()
543 } else if (spi->tx_len >= sizeof(u16)) { in stm32h7_spi_write_txfifo()
544 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
546 writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
547 spi->tx_len -= sizeof(u16); in stm32h7_spi_write_txfifo()
549 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
551 writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
552 spi->tx_len -= sizeof(u8); in stm32h7_spi_write_txfifo()
556 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); in stm32h7_spi_write_txfifo()
561 * @spi: pointer to the spi controller data structure
566 static void stm32f4_spi_read_rx(struct stm32_spi *spi) in stm32f4_spi_read_rx() argument
568 if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) & in stm32f4_spi_read_rx()
570 u32 offs = spi->cur_xferlen - spi->rx_len; in stm32f4_spi_read_rx()
572 if (spi->cur_bpw == 16) { in stm32f4_spi_read_rx()
573 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); in stm32f4_spi_read_rx()
575 *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_read_rx()
576 spi->rx_len -= sizeof(u16); in stm32f4_spi_read_rx()
578 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); in stm32f4_spi_read_rx()
580 *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_read_rx()
581 spi->rx_len -= sizeof(u8); in stm32f4_spi_read_rx()
585 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len); in stm32f4_spi_read_rx()
590 * @spi: pointer to the spi controller data structure
595 static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush) in stm32h7_spi_read_rxfifo() argument
597 u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_read_rxfifo()
601 while ((spi->rx_len > 0) && in stm32h7_spi_read_rxfifo()
604 u32 offs = spi->cur_xferlen - spi->rx_len; in stm32h7_spi_read_rxfifo()
606 if ((spi->rx_len >= sizeof(u32)) || in stm32h7_spi_read_rxfifo()
608 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
610 *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
611 spi->rx_len -= sizeof(u32); in stm32h7_spi_read_rxfifo()
612 } else if ((spi->rx_len >= sizeof(u16)) || in stm32h7_spi_read_rxfifo()
613 (flush && (rxplvl >= 2 || spi->cur_bpw > 8))) { in stm32h7_spi_read_rxfifo()
614 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
616 *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
617 spi->rx_len -= sizeof(u16); in stm32h7_spi_read_rxfifo()
619 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
621 *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
622 spi->rx_len -= sizeof(u8); in stm32h7_spi_read_rxfifo()
625 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_read_rxfifo()
630 dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__, in stm32h7_spi_read_rxfifo()
631 flush ? "(flush)" : "", spi->rx_len); in stm32h7_spi_read_rxfifo()
635 * stm32_spi_enable - Enable SPI controller
636 * @spi: pointer to the spi controller data structure
638 static void stm32_spi_enable(struct stm32_spi *spi) in stm32_spi_enable() argument
640 dev_dbg(spi->dev, "enable controller\n"); in stm32_spi_enable()
642 stm32_spi_set_bits(spi, spi->cfg->regs->en.reg, in stm32_spi_enable()
643 spi->cfg->regs->en.mask); in stm32_spi_enable()
647 * stm32f4_spi_disable - Disable SPI controller
648 * @spi: pointer to the spi controller data structure
650 static void stm32f4_spi_disable(struct stm32_spi *spi) in stm32f4_spi_disable() argument
655 dev_dbg(spi->dev, "disable controller\n"); in stm32f4_spi_disable()
657 spin_lock_irqsave(&spi->lock, flags); in stm32f4_spi_disable()
659 if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) & in stm32f4_spi_disable()
661 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_disable()
666 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXEIE | in stm32f4_spi_disable()
671 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR, in stm32f4_spi_disable()
674 dev_warn(spi->dev, "disabling condition timeout\n"); in stm32f4_spi_disable()
677 if (spi->cur_usedma && spi->dma_tx) in stm32f4_spi_disable()
678 dmaengine_terminate_all(spi->dma_tx); in stm32f4_spi_disable()
679 if (spi->cur_usedma && spi->dma_rx) in stm32f4_spi_disable()
680 dmaengine_terminate_all(spi->dma_rx); in stm32f4_spi_disable()
682 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE); in stm32f4_spi_disable()
684 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN | in stm32f4_spi_disable()
688 readl_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_disable()
689 readl_relaxed(spi->base + STM32F4_SPI_SR); in stm32f4_spi_disable()
691 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_disable()
695 * stm32h7_spi_disable - Disable SPI controller
696 * @spi: pointer to the spi controller data structure
698 * RX-Fifo is flushed when SPI controller is disabled. To prevent any data
706 static void stm32h7_spi_disable(struct stm32_spi *spi) in stm32h7_spi_disable() argument
711 dev_dbg(spi->dev, "disable controller\n"); in stm32h7_spi_disable()
713 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_disable()
715 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1); in stm32h7_spi_disable()
718 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_disable()
723 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32H7_SPI_SR, in stm32h7_spi_disable()
728 spi->base + STM32H7_SPI_CR1); in stm32h7_spi_disable()
730 spi->base + STM32H7_SPI_SR, in stm32h7_spi_disable()
733 dev_warn(spi->dev, in stm32h7_spi_disable()
738 if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0)) in stm32h7_spi_disable()
739 stm32h7_spi_read_rxfifo(spi, true); in stm32h7_spi_disable()
741 if (spi->cur_usedma && spi->dma_tx) in stm32h7_spi_disable()
742 dmaengine_terminate_all(spi->dma_tx); in stm32h7_spi_disable()
743 if (spi->cur_usedma && spi->dma_rx) in stm32h7_spi_disable()
744 dmaengine_terminate_all(spi->dma_rx); in stm32h7_spi_disable()
746 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); in stm32h7_spi_disable()
748 stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN | in stm32h7_spi_disable()
752 writel_relaxed(0, spi->base + STM32H7_SPI_IER); in stm32h7_spi_disable()
753 writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR); in stm32h7_spi_disable()
755 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_disable()
769 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_can_dma() local
771 if (spi->cfg->has_fifo) in stm32_spi_can_dma()
772 dma_size = spi->fifo_size; in stm32_spi_can_dma()
776 dev_dbg(spi->dev, "%s: %s\n", __func__, in stm32_spi_can_dma()
783 * stm32f4_spi_irq_event - Interrupt handler for SPI controller events
785 * @dev_id: SPI controller master interface
790 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32f4_spi_irq_event() local
795 spin_lock_irqsave(&spi->lock, flags); in stm32f4_spi_irq_event()
797 sr = readl_relaxed(spi->base + STM32F4_SPI_SR); in stm32f4_spi_irq_event()
804 if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX || in stm32f4_spi_irq_event()
805 spi->cur_comm == SPI_3WIRE_TX)) { in stm32f4_spi_irq_event()
811 if (!spi->cur_usedma && spi->cur_comm == SPI_FULL_DUPLEX) { in stm32f4_spi_irq_event()
818 dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr); in stm32f4_spi_irq_event()
819 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_irq_event()
824 dev_warn(spi->dev, "Overrun: received value discarded\n"); in stm32f4_spi_irq_event()
827 readl_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_irq_event()
828 readl_relaxed(spi->base + STM32F4_SPI_SR); in stm32f4_spi_irq_event()
840 if (spi->tx_buf) in stm32f4_spi_irq_event()
841 stm32f4_spi_write_tx(spi); in stm32f4_spi_irq_event()
842 if (spi->tx_len == 0) in stm32f4_spi_irq_event()
847 stm32f4_spi_read_rx(spi); in stm32f4_spi_irq_event()
848 if (spi->rx_len == 0) in stm32f4_spi_irq_event()
851 stm32f4_spi_write_tx(spi); in stm32f4_spi_irq_event()
857 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, in stm32f4_spi_irq_event()
861 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_irq_event()
865 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_irq_event()
870 * stm32f4_spi_irq_thread - Thread of interrupt handler for SPI controller
872 * @dev_id: SPI controller master interface
877 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32f4_spi_irq_thread() local
880 stm32f4_spi_disable(spi); in stm32f4_spi_irq_thread()
886 * stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller
888 * @dev_id: SPI controller master interface
893 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32h7_spi_irq_thread() local
898 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_irq_thread()
900 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_irq_thread()
901 ier = readl_relaxed(spi->base + STM32H7_SPI_IER); in stm32h7_spi_irq_thread()
909 * data, before disabling SPI. in stm32h7_spi_irq_thread()
911 if (spi->rx_buf && !spi->cur_usedma) in stm32h7_spi_irq_thread()
915 dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n", in stm32h7_spi_irq_thread()
917 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_irq_thread()
922 dev_warn(spi->dev, "Communication suspended\n"); in stm32h7_spi_irq_thread()
923 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
924 stm32h7_spi_read_rxfifo(spi, false); in stm32h7_spi_irq_thread()
929 if (spi->cur_usedma) in stm32h7_spi_irq_thread()
934 dev_warn(spi->dev, "Mode fault: transfer aborted\n"); in stm32h7_spi_irq_thread()
939 dev_warn(spi->dev, "Overrun: received value discarded\n"); in stm32h7_spi_irq_thread()
940 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
941 stm32h7_spi_read_rxfifo(spi, false); in stm32h7_spi_irq_thread()
946 if (spi->cur_usedma) in stm32h7_spi_irq_thread()
951 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
952 stm32h7_spi_read_rxfifo(spi, true); in stm32h7_spi_irq_thread()
957 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0))) in stm32h7_spi_irq_thread()
958 stm32h7_spi_write_txfifo(spi); in stm32h7_spi_irq_thread()
961 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
962 stm32h7_spi_read_rxfifo(spi, false); in stm32h7_spi_irq_thread()
964 writel_relaxed(mask, spi->base + STM32H7_SPI_IFCR); in stm32h7_spi_irq_thread()
966 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_irq_thread()
970 stm32h7_spi_disable(spi); in stm32h7_spi_irq_thread()
1005 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_prepare_msg() local
1006 struct spi_device *spi_dev = msg->spi; in stm32_spi_prepare_msg()
1011 /* SPI slave device may need time between data frames */ in stm32_spi_prepare_msg()
1012 spi->cur_midi = 0; in stm32_spi_prepare_msg()
1013 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi)) in stm32_spi_prepare_msg()
1014 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi); in stm32_spi_prepare_msg()
1017 setb |= spi->cfg->regs->cpol.mask; in stm32_spi_prepare_msg()
1019 clrb |= spi->cfg->regs->cpol.mask; in stm32_spi_prepare_msg()
1022 setb |= spi->cfg->regs->cpha.mask; in stm32_spi_prepare_msg()
1024 clrb |= spi->cfg->regs->cpha.mask; in stm32_spi_prepare_msg()
1027 setb |= spi->cfg->regs->lsb_first.mask; in stm32_spi_prepare_msg()
1029 clrb |= spi->cfg->regs->lsb_first.mask; in stm32_spi_prepare_msg()
1031 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n", in stm32_spi_prepare_msg()
1037 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_prepare_msg()
1042 (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) & in stm32_spi_prepare_msg()
1044 spi->base + spi->cfg->regs->cpol.reg); in stm32_spi_prepare_msg()
1046 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_prepare_msg()
1058 struct stm32_spi *spi = data; in stm32f4_spi_dma_tx_cb() local
1060 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { in stm32f4_spi_dma_tx_cb()
1061 spi_finalize_current_transfer(spi->master); in stm32f4_spi_dma_tx_cb()
1062 stm32f4_spi_disable(spi); in stm32f4_spi_dma_tx_cb()
1073 struct stm32_spi *spi = data; in stm32f4_spi_dma_rx_cb() local
1075 spi_finalize_current_transfer(spi->master); in stm32f4_spi_dma_rx_cb()
1076 stm32f4_spi_disable(spi); in stm32f4_spi_dma_rx_cb()
1087 struct stm32_spi *spi = data; in stm32h7_spi_dma_cb() local
1091 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_dma_cb()
1093 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_dma_cb()
1095 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_dma_cb()
1098 dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr); in stm32h7_spi_dma_cb()
1107 static void stm32_spi_dma_config(struct stm32_spi *spi, in stm32_spi_dma_config() argument
1114 if (spi->cur_bpw <= 8) in stm32_spi_dma_config()
1116 else if (spi->cur_bpw <= 16) in stm32_spi_dma_config()
1121 if (spi->cfg->has_fifo) { in stm32_spi_dma_config()
1123 if (spi->cur_fthlv == 2) in stm32_spi_dma_config()
1126 maxburst = spi->cur_fthlv; in stm32_spi_dma_config()
1134 dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg; in stm32_spi_dma_config()
1138 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n", in stm32_spi_dma_config()
1141 dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg; in stm32_spi_dma_config()
1145 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n", in stm32_spi_dma_config()
1157 static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi) in stm32f4_spi_transfer_one_irq() argument
1163 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { in stm32f4_spi_transfer_one_irq()
1165 } else if (spi->cur_comm == SPI_FULL_DUPLEX) { in stm32f4_spi_transfer_one_irq()
1175 spin_lock_irqsave(&spi->lock, flags); in stm32f4_spi_transfer_one_irq()
1177 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, cr2); in stm32f4_spi_transfer_one_irq()
1179 stm32_spi_enable(spi); in stm32f4_spi_transfer_one_irq()
1182 if (spi->tx_buf) in stm32f4_spi_transfer_one_irq()
1183 stm32f4_spi_write_tx(spi); in stm32f4_spi_transfer_one_irq()
1185 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_transfer_one_irq()
1197 static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi) in stm32h7_spi_transfer_one_irq() argument
1203 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */ in stm32h7_spi_transfer_one_irq()
1205 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */ in stm32h7_spi_transfer_one_irq()
1207 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */ in stm32h7_spi_transfer_one_irq()
1214 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_transfer_one_irq()
1216 stm32_spi_enable(spi); in stm32h7_spi_transfer_one_irq()
1219 if (spi->tx_buf) in stm32h7_spi_transfer_one_irq()
1220 stm32h7_spi_write_txfifo(spi); in stm32h7_spi_transfer_one_irq()
1222 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART); in stm32h7_spi_transfer_one_irq()
1224 writel_relaxed(ier, spi->base + STM32H7_SPI_IER); in stm32h7_spi_transfer_one_irq()
1226 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_transfer_one_irq()
1232 * stm32f4_spi_transfer_one_dma_start - Set SPI driver registers to start
1235 static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi) in stm32f4_spi_transfer_one_dma_start() argument
1238 if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX || in stm32f4_spi_transfer_one_dma_start()
1239 spi->cur_comm == SPI_FULL_DUPLEX) { in stm32f4_spi_transfer_one_dma_start()
1245 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_ERRIE); in stm32f4_spi_transfer_one_dma_start()
1248 stm32_spi_enable(spi); in stm32f4_spi_transfer_one_dma_start()
1252 * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start
1255 static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi) in stm32h7_spi_transfer_one_dma_start() argument
1258 stm32_spi_set_bits(spi, STM32H7_SPI_IER, STM32H7_SPI_IER_EOTIE | in stm32h7_spi_transfer_one_dma_start()
1263 stm32_spi_enable(spi); in stm32h7_spi_transfer_one_dma_start()
1265 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART); in stm32h7_spi_transfer_one_dma_start()
1274 static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, in stm32_spi_transfer_one_dma() argument
1281 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1284 if (spi->rx_buf && spi->dma_rx) { in stm32_spi_transfer_one_dma()
1285 stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM); in stm32_spi_transfer_one_dma()
1286 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf); in stm32_spi_transfer_one_dma()
1289 stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg, in stm32_spi_transfer_one_dma()
1290 spi->cfg->regs->dma_rx_en.mask); in stm32_spi_transfer_one_dma()
1293 spi->dma_rx, xfer->rx_sg.sgl, in stm32_spi_transfer_one_dma()
1300 if (spi->tx_buf && spi->dma_tx) { in stm32_spi_transfer_one_dma()
1301 stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV); in stm32_spi_transfer_one_dma()
1302 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf); in stm32_spi_transfer_one_dma()
1305 spi->dma_tx, xfer->tx_sg.sgl, in stm32_spi_transfer_one_dma()
1311 if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) || in stm32_spi_transfer_one_dma()
1312 (spi->rx_buf && spi->dma_rx && !rx_dma_desc)) in stm32_spi_transfer_one_dma()
1315 if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc)) in stm32_spi_transfer_one_dma()
1319 rx_dma_desc->callback = spi->cfg->dma_rx_cb; in stm32_spi_transfer_one_dma()
1320 rx_dma_desc->callback_param = spi; in stm32_spi_transfer_one_dma()
1323 dev_err(spi->dev, "Rx DMA submit failed\n"); in stm32_spi_transfer_one_dma()
1327 dma_async_issue_pending(spi->dma_rx); in stm32_spi_transfer_one_dma()
1331 if (spi->cur_comm == SPI_SIMPLEX_TX || in stm32_spi_transfer_one_dma()
1332 spi->cur_comm == SPI_3WIRE_TX) { in stm32_spi_transfer_one_dma()
1333 tx_dma_desc->callback = spi->cfg->dma_tx_cb; in stm32_spi_transfer_one_dma()
1334 tx_dma_desc->callback_param = spi; in stm32_spi_transfer_one_dma()
1338 dev_err(spi->dev, "Tx DMA submit failed\n"); in stm32_spi_transfer_one_dma()
1342 dma_async_issue_pending(spi->dma_tx); in stm32_spi_transfer_one_dma()
1345 stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg, in stm32_spi_transfer_one_dma()
1346 spi->cfg->regs->dma_tx_en.mask); in stm32_spi_transfer_one_dma()
1349 spi->cfg->transfer_one_dma_start(spi); in stm32_spi_transfer_one_dma()
1351 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1356 if (spi->dma_rx) in stm32_spi_transfer_one_dma()
1357 dmaengine_terminate_all(spi->dma_rx); in stm32_spi_transfer_one_dma()
1360 stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg, in stm32_spi_transfer_one_dma()
1361 spi->cfg->regs->dma_rx_en.mask); in stm32_spi_transfer_one_dma()
1363 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1365 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n"); in stm32_spi_transfer_one_dma()
1367 spi->cur_usedma = false; in stm32_spi_transfer_one_dma()
1368 return spi->cfg->transfer_one_irq(spi); in stm32_spi_transfer_one_dma()
1373 * @spi: pointer to the spi controller data structure
1375 static void stm32f4_spi_set_bpw(struct stm32_spi *spi) in stm32f4_spi_set_bpw() argument
1377 if (spi->cur_bpw == 16) in stm32f4_spi_set_bpw()
1378 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF); in stm32f4_spi_set_bpw()
1380 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF); in stm32f4_spi_set_bpw()
1385 * @spi: pointer to the spi controller data structure
1387 static void stm32h7_spi_set_bpw(struct stm32_spi *spi) in stm32h7_spi_set_bpw() argument
1392 bpw = spi->cur_bpw - 1; in stm32h7_spi_set_bpw()
1398 spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi); in stm32h7_spi_set_bpw()
1399 fthlv = spi->cur_fthlv - 1; in stm32h7_spi_set_bpw()
1406 (readl_relaxed(spi->base + STM32H7_SPI_CFG1) & in stm32h7_spi_set_bpw()
1408 spi->base + STM32H7_SPI_CFG1); in stm32h7_spi_set_bpw()
1413 * @spi: pointer to the spi controller data structure
1416 static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv) in stm32_spi_set_mbr() argument
1420 clrb |= spi->cfg->regs->br.mask; in stm32_spi_set_mbr()
1421 setb |= ((u32)mbrdiv << spi->cfg->regs->br.shift) & in stm32_spi_set_mbr()
1422 spi->cfg->regs->br.mask; in stm32_spi_set_mbr()
1424 writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) & in stm32_spi_set_mbr()
1426 spi->base + spi->cfg->regs->br.reg); in stm32_spi_set_mbr()
1431 * @spi_dev: pointer to the spi device
1432 * transfer: pointer to spi transfer
1442 * is forbidden and unvalidated by SPI subsystem so depending in stm32_spi_communication_type()
1462 * @spi: pointer to the spi controller data structure
1465 static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type) in stm32f4_spi_set_mode() argument
1468 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, in stm32f4_spi_set_mode()
1472 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, in stm32f4_spi_set_mode()
1484 * @spi: pointer to the spi controller data structure
1487 static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type) in stm32h7_spi_set_mode() argument
1494 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR); in stm32h7_spi_set_mode()
1497 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR); in stm32h7_spi_set_mode()
1511 (readl_relaxed(spi->base + STM32H7_SPI_CFG2) & in stm32h7_spi_set_mode()
1513 spi->base + STM32H7_SPI_CFG2); in stm32h7_spi_set_mode()
1521 * @spi: pointer to the spi controller data structure
1524 static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len) in stm32h7_spi_data_idleness() argument
1529 if ((len > 1) && (spi->cur_midi > 0)) { in stm32h7_spi_data_idleness()
1530 u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed); in stm32h7_spi_data_idleness()
1531 u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns), in stm32h7_spi_data_idleness()
1535 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n", in stm32h7_spi_data_idleness()
1541 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) & in stm32h7_spi_data_idleness()
1543 spi->base + STM32H7_SPI_CFG2); in stm32h7_spi_data_idleness()
1548 * @spi: pointer to the spi controller data structure
1551 static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words) in stm32h7_spi_number_of_data() argument
1559 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CR2) & in stm32h7_spi_number_of_data()
1561 spi->base + STM32H7_SPI_CR2); in stm32h7_spi_number_of_data()
1574 static int stm32_spi_transfer_one_setup(struct stm32_spi *spi, in stm32_spi_transfer_one_setup() argument
1582 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_transfer_one_setup()
1584 if (spi->cur_bpw != transfer->bits_per_word) { in stm32_spi_transfer_one_setup()
1585 spi->cur_bpw = transfer->bits_per_word; in stm32_spi_transfer_one_setup()
1586 spi->cfg->set_bpw(spi); in stm32_spi_transfer_one_setup()
1589 if (spi->cur_speed != transfer->speed_hz) { in stm32_spi_transfer_one_setup()
1592 /* Update spi->cur_speed with real clock speed */ in stm32_spi_transfer_one_setup()
1593 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz, in stm32_spi_transfer_one_setup()
1594 spi->cfg->baud_rate_div_min, in stm32_spi_transfer_one_setup()
1595 spi->cfg->baud_rate_div_max); in stm32_spi_transfer_one_setup()
1601 transfer->speed_hz = spi->cur_speed; in stm32_spi_transfer_one_setup()
1602 stm32_spi_set_mbr(spi, mbr); in stm32_spi_transfer_one_setup()
1606 if (spi->cur_comm != comm_type) { in stm32_spi_transfer_one_setup()
1607 ret = spi->cfg->set_mode(spi, comm_type); in stm32_spi_transfer_one_setup()
1612 spi->cur_comm = comm_type; in stm32_spi_transfer_one_setup()
1615 if (spi->cfg->set_data_idleness) in stm32_spi_transfer_one_setup()
1616 spi->cfg->set_data_idleness(spi, transfer->len); in stm32_spi_transfer_one_setup()
1618 if (spi->cur_bpw <= 8) in stm32_spi_transfer_one_setup()
1620 else if (spi->cur_bpw <= 16) in stm32_spi_transfer_one_setup()
1625 if (spi->cfg->set_number_of_data) { in stm32_spi_transfer_one_setup()
1626 ret = spi->cfg->set_number_of_data(spi, nb_words); in stm32_spi_transfer_one_setup()
1631 spi->cur_xferlen = transfer->len; in stm32_spi_transfer_one_setup()
1633 dev_dbg(spi->dev, "transfer communication mode set to %d\n", in stm32_spi_transfer_one_setup()
1634 spi->cur_comm); in stm32_spi_transfer_one_setup()
1635 dev_dbg(spi->dev, in stm32_spi_transfer_one_setup()
1637 spi->cur_bpw, spi->cur_fthlv); in stm32_spi_transfer_one_setup()
1638 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed); in stm32_spi_transfer_one_setup()
1639 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n", in stm32_spi_transfer_one_setup()
1640 spi->cur_xferlen, nb_words); in stm32_spi_transfer_one_setup()
1641 dev_dbg(spi->dev, "dma %s\n", in stm32_spi_transfer_one_setup()
1642 (spi->cur_usedma) ? "enabled" : "disabled"); in stm32_spi_transfer_one_setup()
1645 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_setup()
1660 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_transfer_one() local
1663 spi->tx_buf = transfer->tx_buf; in stm32_spi_transfer_one()
1664 spi->rx_buf = transfer->rx_buf; in stm32_spi_transfer_one()
1665 spi->tx_len = spi->tx_buf ? transfer->len : 0; in stm32_spi_transfer_one()
1666 spi->rx_len = spi->rx_buf ? transfer->len : 0; in stm32_spi_transfer_one()
1668 spi->cur_usedma = (master->can_dma && in stm32_spi_transfer_one()
1671 ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer); in stm32_spi_transfer_one()
1673 dev_err(spi->dev, "SPI transfer setup failed\n"); in stm32_spi_transfer_one()
1677 if (spi->cur_usedma) in stm32_spi_transfer_one()
1678 return stm32_spi_transfer_one_dma(spi, transfer); in stm32_spi_transfer_one()
1680 return spi->cfg->transfer_one_irq(spi); in stm32_spi_transfer_one()
1689 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_unprepare_msg() local
1691 spi->cfg->disable(spi); in stm32_spi_unprepare_msg()
1697 * stm32f4_spi_config - Configure SPI controller as SPI master
1699 static int stm32f4_spi_config(struct stm32_spi *spi) in stm32f4_spi_config() argument
1703 spin_lock_irqsave(&spi->lock, flags); in stm32f4_spi_config()
1706 stm32_spi_clr_bits(spi, STM32F4_SPI_I2SCFGR, in stm32f4_spi_config()
1716 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SSI | in stm32f4_spi_config()
1721 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_config()
1727 * stm32h7_spi_config - Configure SPI controller as SPI master
1729 static int stm32h7_spi_config(struct stm32_spi *spi) in stm32h7_spi_config() argument
1733 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_config()
1736 stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR, in stm32h7_spi_config()
1744 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SSI | in stm32h7_spi_config()
1754 stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_MASTER | in stm32h7_spi_config()
1758 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_config()
1802 { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
1803 { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
1811 struct stm32_spi *spi; in stm32_spi_probe() local
1817 dev_err(&pdev->dev, "spi master allocation failed\n"); in stm32_spi_probe()
1822 spi = spi_master_get_devdata(master); in stm32_spi_probe()
1823 spi->dev = &pdev->dev; in stm32_spi_probe()
1824 spi->master = master; in stm32_spi_probe()
1825 spin_lock_init(&spi->lock); in stm32_spi_probe()
1827 spi->cfg = (const struct stm32_spi_cfg *) in stm32_spi_probe()
1832 spi->base = devm_ioremap_resource(&pdev->dev, res); in stm32_spi_probe()
1833 if (IS_ERR(spi->base)) { in stm32_spi_probe()
1834 ret = PTR_ERR(spi->base); in stm32_spi_probe()
1838 spi->phys_addr = (dma_addr_t)res->start; in stm32_spi_probe()
1840 spi->irq = platform_get_irq(pdev, 0); in stm32_spi_probe()
1841 if (spi->irq <= 0) { in stm32_spi_probe()
1842 ret = spi->irq; in stm32_spi_probe()
1847 ret = devm_request_threaded_irq(&pdev->dev, spi->irq, in stm32_spi_probe()
1848 spi->cfg->irq_handler_event, in stm32_spi_probe()
1849 spi->cfg->irq_handler_thread, in stm32_spi_probe()
1852 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq, in stm32_spi_probe()
1857 spi->clk = devm_clk_get(&pdev->dev, NULL); in stm32_spi_probe()
1858 if (IS_ERR(spi->clk)) { in stm32_spi_probe()
1859 ret = PTR_ERR(spi->clk); in stm32_spi_probe()
1864 ret = clk_prepare_enable(spi->clk); in stm32_spi_probe()
1869 spi->clk_rate = clk_get_rate(spi->clk); in stm32_spi_probe()
1870 if (!spi->clk_rate) { in stm32_spi_probe()
1876 spi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); in stm32_spi_probe()
1877 if (!IS_ERR(spi->rst)) { in stm32_spi_probe()
1878 reset_control_assert(spi->rst); in stm32_spi_probe()
1880 reset_control_deassert(spi->rst); in stm32_spi_probe()
1883 if (spi->cfg->has_fifo) in stm32_spi_probe()
1884 spi->fifo_size = spi->cfg->get_fifo_size(spi); in stm32_spi_probe()
1886 ret = spi->cfg->config(spi); in stm32_spi_probe()
1898 master->bits_per_word_mask = spi->cfg->get_bpw_mask(spi); in stm32_spi_probe()
1899 master->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min; in stm32_spi_probe()
1900 master->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max; in stm32_spi_probe()
1906 spi->dma_tx = dma_request_slave_channel(spi->dev, "tx"); in stm32_spi_probe()
1907 if (!spi->dma_tx) in stm32_spi_probe()
1910 master->dma_tx = spi->dma_tx; in stm32_spi_probe()
1912 spi->dma_rx = dma_request_slave_channel(spi->dev, "rx"); in stm32_spi_probe()
1913 if (!spi->dma_rx) in stm32_spi_probe()
1916 master->dma_rx = spi->dma_rx; in stm32_spi_probe()
1918 if (spi->dma_tx || spi->dma_rx) in stm32_spi_probe()
1926 dev_err(&pdev->dev, "spi master registration failed: %d\n", in stm32_spi_probe()
1959 if (spi->dma_tx) in stm32_spi_probe()
1960 dma_release_channel(spi->dma_tx); in stm32_spi_probe()
1961 if (spi->dma_rx) in stm32_spi_probe()
1962 dma_release_channel(spi->dma_rx); in stm32_spi_probe()
1966 clk_disable_unprepare(spi->clk); in stm32_spi_probe()
1976 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_remove() local
1978 spi->cfg->disable(spi); in stm32_spi_remove()
1985 clk_disable_unprepare(spi->clk); in stm32_spi_remove()
1996 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_runtime_suspend() local
1998 clk_disable_unprepare(spi->clk); in stm32_spi_runtime_suspend()
2006 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_runtime_resume() local
2008 return clk_prepare_enable(spi->clk); in stm32_spi_runtime_resume()
2028 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_resume() local
2037 clk_disable_unprepare(spi->clk); in stm32_spi_resume()
2062 MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver");