Lines Matching +full:rx +full:- +full:level +full:- +full:trig
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2008-2012 ST-Ericsson AB
11 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
31 #include <linux/dma-mapping.h>
93 * SSP Control Register 0 - SSP_CR0
111 * SSP Control Register 0 - SSP_CR1
131 * SSP Status Register - SSP_SR
140 * SSP Clock Prescale Register - SSP_CPSR
145 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
153 * SSP Raw Interrupt Status Register - SSP_RIS
165 * SSP Masked Interrupt Status Register - SSP_MIS
177 * SSP Interrupt Clear Register - SSP_ICR
185 * SSP DMA Control Register - SSP_DMACR
193 * SSP Chip Select Control Register - SSP_CSR
199 * SSP Integration Test control Register - SSP_ITCR
205 * SSP Integration Test Input Register - SSP_ITIP
215 * SSP Integration Test output Register - SSP_ITOP
233 * SSP Test Data Register - SSP_TDR
246 #define STATE_ERROR ((void *) -1)
247 #define STATE_TIMEOUT ((void *) -2)
250 * SSP State - Whether Enabled or Disabled
256 * SSP DMA State - Whether DMA Enabled or Disabled
312 * struct vendor_data - vendor-specific config parameters
333 * struct pl022 - This is the private SSP driver data structure
340 * @master_info: controller-specific data from machine setup
351 * @rx: current position in RX buffer to be written
352 * @rx_end: end position in RX buffer to be written
355 * @exp_fifo_level: expected FIFO level
356 * @dma_rx_channel: optional channel for RX DMA
358 * @sgt_rx: scattertable for the RX transfer
372 /* Message per-transfer pump */
380 void *rx; member
401 * struct chip_data - To maintain runtime state of SSP for each client chip
402 * @cr0: Value of control register CR0 of SSP - on later ST variants this
431 * null_cs_control - Dummy chip select function
443 * internal_cs_control - Control chip select signals via SSP_CSR.
455 tmp = readw(SSP_CSR(pl022->virtbase)); in internal_cs_control()
457 tmp &= ~BIT(pl022->cur_cs); in internal_cs_control()
459 tmp |= BIT(pl022->cur_cs); in internal_cs_control()
460 writew(tmp, SSP_CSR(pl022->virtbase)); in internal_cs_control()
465 if (pl022->vendor->internal_cs_ctrl) in pl022_cs_control()
467 else if (gpio_is_valid(pl022->cur_cs)) in pl022_cs_control()
468 gpio_set_value(pl022->cur_cs, command); in pl022_cs_control()
470 pl022->cur_chip->cs_control(command); in pl022_cs_control()
474 * giveback - current spi_message is over, schedule next message and call
476 * set message->status; dma and pio irqs are blocked
482 pl022->next_msg_cs_active = false; in giveback()
484 last_transfer = list_last_entry(&pl022->cur_msg->transfers, in giveback()
488 if (last_transfer->delay_usecs) in giveback()
493 udelay(last_transfer->delay_usecs); in giveback()
495 if (!last_transfer->cs_change) { in giveback()
504 * after calling msg->complete (below) the driver that in giveback()
509 next_msg = spi_get_next_queued_message(pl022->master); in giveback()
515 if (next_msg && next_msg->spi != pl022->cur_msg->spi) in giveback()
517 if (!next_msg || pl022->cur_msg->state == STATE_ERROR) in giveback()
520 pl022->next_msg_cs_active = true; in giveback()
524 pl022->cur_msg = NULL; in giveback()
525 pl022->cur_transfer = NULL; in giveback()
526 pl022->cur_chip = NULL; in giveback()
529 writew((readw(SSP_CR1(pl022->virtbase)) & in giveback()
530 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); in giveback()
532 spi_finalize_current_message(pl022->master); in giveback()
536 * flush - flush the FIFO to reach a clean state
543 dev_dbg(&pl022->adev->dev, "flush\n"); in flush()
545 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) in flush()
546 readw(SSP_DR(pl022->virtbase)); in flush()
547 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); in flush()
549 pl022->exp_fifo_level = 0; in flush()
555 * restore_state - Load configuration of current chip
560 struct chip_data *chip = pl022->cur_chip; in restore_state()
562 if (pl022->vendor->extended_cr) in restore_state()
563 writel(chip->cr0, SSP_CR0(pl022->virtbase)); in restore_state()
565 writew(chip->cr0, SSP_CR0(pl022->virtbase)); in restore_state()
566 writew(chip->cr1, SSP_CR1(pl022->virtbase)); in restore_state()
567 writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); in restore_state()
568 writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); in restore_state()
569 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); in restore_state()
570 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); in restore_state()
645 * load_ssp_default_config - Load default configuration for SSP
650 if (pl022->vendor->pl023) { in load_ssp_default_config()
651 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); in load_ssp_default_config()
652 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); in load_ssp_default_config()
653 } else if (pl022->vendor->extended_cr) { in load_ssp_default_config()
654 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); in load_ssp_default_config()
655 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); in load_ssp_default_config()
657 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); in load_ssp_default_config()
658 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); in load_ssp_default_config()
660 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); in load_ssp_default_config()
661 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); in load_ssp_default_config()
662 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); in load_ssp_default_config()
663 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); in load_ssp_default_config()
667 * This will write to TX and read from RX according to the parameters
680 * unused RX FIFO fill length, regardless of what the TX in readwriter()
683 dev_dbg(&pl022->adev->dev, in readwriter()
684 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", in readwriter()
685 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); in readwriter()
688 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) in readwriter()
689 && (pl022->rx < pl022->rx_end)) { in readwriter()
690 switch (pl022->read) { in readwriter()
692 readw(SSP_DR(pl022->virtbase)); in readwriter()
695 *(u8 *) (pl022->rx) = in readwriter()
696 readw(SSP_DR(pl022->virtbase)) & 0xFFU; in readwriter()
699 *(u16 *) (pl022->rx) = in readwriter()
700 (u16) readw(SSP_DR(pl022->virtbase)); in readwriter()
703 *(u32 *) (pl022->rx) = in readwriter()
704 readl(SSP_DR(pl022->virtbase)); in readwriter()
707 pl022->rx += (pl022->cur_chip->n_bytes); in readwriter()
708 pl022->exp_fifo_level--; in readwriter()
711 * Write as much as possible up to the RX FIFO size in readwriter()
713 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) in readwriter()
714 && (pl022->tx < pl022->tx_end)) { in readwriter()
715 switch (pl022->write) { in readwriter()
717 writew(0x0, SSP_DR(pl022->virtbase)); in readwriter()
720 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); in readwriter()
723 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); in readwriter()
726 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); in readwriter()
729 pl022->tx += (pl022->cur_chip->n_bytes); in readwriter()
730 pl022->exp_fifo_level++; in readwriter()
732 * This inner reader takes care of things appearing in the RX in readwriter()
735 * and then things are continuously clocked into the RX FIFO. in readwriter()
737 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) in readwriter()
738 && (pl022->rx < pl022->rx_end)) { in readwriter()
739 switch (pl022->read) { in readwriter()
741 readw(SSP_DR(pl022->virtbase)); in readwriter()
744 *(u8 *) (pl022->rx) = in readwriter()
745 readw(SSP_DR(pl022->virtbase)) & 0xFFU; in readwriter()
748 *(u16 *) (pl022->rx) = in readwriter()
749 (u16) readw(SSP_DR(pl022->virtbase)); in readwriter()
752 *(u32 *) (pl022->rx) = in readwriter()
753 readl(SSP_DR(pl022->virtbase)); in readwriter()
756 pl022->rx += (pl022->cur_chip->n_bytes); in readwriter()
757 pl022->exp_fifo_level--; in readwriter()
761 * When we exit here the TX FIFO should be full and the RX FIFO in readwriter()
767 * next_transfer - Move to the Next transfer in the current spi message
777 struct spi_message *msg = pl022->cur_msg; in next_transfer()
778 struct spi_transfer *trans = pl022->cur_transfer; in next_transfer()
781 if (trans->transfer_list.next != &msg->transfers) { in next_transfer()
782 pl022->cur_transfer = in next_transfer()
783 list_entry(trans->transfer_list.next, in next_transfer()
798 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, in unmap_free_dma_scatter()
799 pl022->sgt_tx.nents, DMA_TO_DEVICE); in unmap_free_dma_scatter()
800 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, in unmap_free_dma_scatter()
801 pl022->sgt_rx.nents, DMA_FROM_DEVICE); in unmap_free_dma_scatter()
802 sg_free_table(&pl022->sgt_rx); in unmap_free_dma_scatter()
803 sg_free_table(&pl022->sgt_tx); in unmap_free_dma_scatter()
809 struct spi_message *msg = pl022->cur_msg; in dma_callback()
811 BUG_ON(!pl022->sgt_rx.sgl); in dma_callback()
824 dma_sync_sg_for_cpu(&pl022->adev->dev, in dma_callback()
825 pl022->sgt_rx.sgl, in dma_callback()
826 pl022->sgt_rx.nents, in dma_callback()
829 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { in dma_callback()
830 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); in dma_callback()
831 print_hex_dump(KERN_ERR, "SPI RX: ", in dma_callback()
839 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { in dma_callback()
840 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); in dma_callback()
855 msg->actual_length += pl022->cur_transfer->len; in dma_callback()
857 msg->state = next_transfer(pl022); in dma_callback()
858 if (msg->state != STATE_DONE && pl022->cur_transfer->cs_change) in dma_callback()
860 tasklet_schedule(&pl022->pump_transfers); in dma_callback()
875 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { in setup_dma_scatter()
882 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) in setup_dma_scatter()
885 mapbytes = PAGE_SIZE - offset_in_page(bufp); in setup_dma_scatter()
889 bytesleft -= mapbytes; in setup_dma_scatter()
890 dev_dbg(&pl022->adev->dev, in setup_dma_scatter()
891 "set RX/TX target page @ %p, %d bytes, %d left\n", in setup_dma_scatter()
896 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { in setup_dma_scatter()
901 sg_set_page(sg, virt_to_page(pl022->dummypage), in setup_dma_scatter()
903 bytesleft -= mapbytes; in setup_dma_scatter()
904 dev_dbg(&pl022->adev->dev, in setup_dma_scatter()
905 "set RX/TX to dummy page %d bytes, %d left\n", in setup_dma_scatter()
914 * configure_dma - configures the channels for the next transfer
920 .src_addr = SSP_DR(pl022->phybase), in configure_dma()
925 .dst_addr = SSP_DR(pl022->phybase), in configure_dma()
932 struct dma_chan *rxchan = pl022->dma_rx_channel; in configure_dma()
933 struct dma_chan *txchan = pl022->dma_tx_channel; in configure_dma()
939 return -ENODEV; in configure_dma()
942 * If supplied, the DMA burstsize should equal the FIFO trigger level. in configure_dma()
943 * Notice that the DMA engine uses one-to-one mapping. Since we can in configure_dma()
947 switch (pl022->rx_lev_trig) { in configure_dma()
964 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; in configure_dma()
968 switch (pl022->tx_lev_trig) { in configure_dma()
985 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; in configure_dma()
989 switch (pl022->read) { in configure_dma()
1005 switch (pl022->write) { in configure_dma()
1032 pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE); in configure_dma()
1033 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); in configure_dma()
1035 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC); in configure_dma()
1039 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC); in configure_dma()
1043 /* Fill in the scatterlists for the RX+TX buffers */ in configure_dma()
1044 setup_dma_scatter(pl022, pl022->rx, in configure_dma()
1045 pl022->cur_transfer->len, &pl022->sgt_rx); in configure_dma()
1046 setup_dma_scatter(pl022, pl022->tx, in configure_dma()
1047 pl022->cur_transfer->len, &pl022->sgt_tx); in configure_dma()
1050 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, in configure_dma()
1051 pl022->sgt_rx.nents, DMA_FROM_DEVICE); in configure_dma()
1055 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, in configure_dma()
1056 pl022->sgt_tx.nents, DMA_TO_DEVICE); in configure_dma()
1062 pl022->sgt_rx.sgl, in configure_dma()
1070 pl022->sgt_tx.sgl, in configure_dma()
1077 /* Put the callback on the RX transfer only, that should finish last */ in configure_dma()
1078 rxdesc->callback = dma_callback; in configure_dma()
1079 rxdesc->callback_param = pl022; in configure_dma()
1081 /* Submit and fire RX and TX with TX last so we're ready to read! */ in configure_dma()
1086 pl022->dma_running = true; in configure_dma()
1094 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, in configure_dma()
1095 pl022->sgt_tx.nents, DMA_TO_DEVICE); in configure_dma()
1097 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, in configure_dma()
1098 pl022->sgt_rx.nents, DMA_FROM_DEVICE); in configure_dma()
1100 sg_free_table(&pl022->sgt_tx); in configure_dma()
1102 sg_free_table(&pl022->sgt_rx); in configure_dma()
1104 return -ENOMEM; in configure_dma()
1115 * We need both RX and TX channels to do DMA, else do none in pl022_dma_probe()
1118 pl022->dma_rx_channel = dma_request_channel(mask, in pl022_dma_probe()
1119 pl022->master_info->dma_filter, in pl022_dma_probe()
1120 pl022->master_info->dma_rx_param); in pl022_dma_probe()
1121 if (!pl022->dma_rx_channel) { in pl022_dma_probe()
1122 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); in pl022_dma_probe()
1126 pl022->dma_tx_channel = dma_request_channel(mask, in pl022_dma_probe()
1127 pl022->master_info->dma_filter, in pl022_dma_probe()
1128 pl022->master_info->dma_tx_param); in pl022_dma_probe()
1129 if (!pl022->dma_tx_channel) { in pl022_dma_probe()
1130 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); in pl022_dma_probe()
1134 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); in pl022_dma_probe()
1135 if (!pl022->dummypage) in pl022_dma_probe()
1138 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", in pl022_dma_probe()
1139 dma_chan_name(pl022->dma_rx_channel), in pl022_dma_probe()
1140 dma_chan_name(pl022->dma_tx_channel)); in pl022_dma_probe()
1145 dma_release_channel(pl022->dma_tx_channel); in pl022_dma_probe()
1147 dma_release_channel(pl022->dma_rx_channel); in pl022_dma_probe()
1148 pl022->dma_rx_channel = NULL; in pl022_dma_probe()
1150 dev_err(&pl022->adev->dev, in pl022_dma_probe()
1152 return -ENODEV; in pl022_dma_probe()
1157 struct device *dev = &pl022->adev->dev; in pl022_dma_autoprobe()
1162 chan = dma_request_slave_channel_reason(dev, "rx"); in pl022_dma_autoprobe()
1168 pl022->dma_rx_channel = chan; in pl022_dma_autoprobe()
1176 pl022->dma_tx_channel = chan; in pl022_dma_autoprobe()
1178 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); in pl022_dma_autoprobe()
1179 if (!pl022->dummypage) { in pl022_dma_autoprobe()
1180 err = -ENOMEM; in pl022_dma_autoprobe()
1187 dma_release_channel(pl022->dma_tx_channel); in pl022_dma_autoprobe()
1188 pl022->dma_tx_channel = NULL; in pl022_dma_autoprobe()
1190 dma_release_channel(pl022->dma_rx_channel); in pl022_dma_autoprobe()
1191 pl022->dma_rx_channel = NULL; in pl022_dma_autoprobe()
1198 struct dma_chan *rxchan = pl022->dma_rx_channel; in terminate_dma()
1199 struct dma_chan *txchan = pl022->dma_tx_channel; in terminate_dma()
1204 pl022->dma_running = false; in terminate_dma()
1209 if (pl022->dma_running) in pl022_dma_remove()
1211 if (pl022->dma_tx_channel) in pl022_dma_remove()
1212 dma_release_channel(pl022->dma_tx_channel); in pl022_dma_remove()
1213 if (pl022->dma_rx_channel) in pl022_dma_remove()
1214 dma_release_channel(pl022->dma_rx_channel); in pl022_dma_remove()
1215 kfree(pl022->dummypage); in pl022_dma_remove()
1221 return -ENODEV; in configure_dma()
1240 * pl022_interrupt_handler - Interrupt handler for SSP controller
1246 * calling giveback(). Otherwise it reads data from RX FIFO till there is no
1253 struct spi_message *msg = pl022->cur_msg; in pl022_interrupt_handler()
1257 dev_err(&pl022->adev->dev, in pl022_interrupt_handler()
1264 irq_status = readw(SSP_MIS(pl022->virtbase)); in pl022_interrupt_handler()
1276 * Overrun interrupt - bail out since our Data has been in pl022_interrupt_handler()
1279 dev_err(&pl022->adev->dev, "FIFO overrun\n"); in pl022_interrupt_handler()
1280 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) in pl022_interrupt_handler()
1281 dev_err(&pl022->adev->dev, in pl022_interrupt_handler()
1290 SSP_IMSC(pl022->virtbase)); in pl022_interrupt_handler()
1291 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); in pl022_interrupt_handler()
1292 writew((readw(SSP_CR1(pl022->virtbase)) & in pl022_interrupt_handler()
1293 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); in pl022_interrupt_handler()
1294 msg->state = STATE_ERROR; in pl022_interrupt_handler()
1297 tasklet_schedule(&pl022->pump_transfers); in pl022_interrupt_handler()
1303 if (pl022->tx == pl022->tx_end) { in pl022_interrupt_handler()
1305 writew((readw(SSP_IMSC(pl022->virtbase)) & in pl022_interrupt_handler()
1307 SSP_IMSC(pl022->virtbase)); in pl022_interrupt_handler()
1312 * we can conclude the entire transaction once RX is complete. in pl022_interrupt_handler()
1315 if (pl022->rx >= pl022->rx_end) { in pl022_interrupt_handler()
1317 SSP_IMSC(pl022->virtbase)); in pl022_interrupt_handler()
1318 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); in pl022_interrupt_handler()
1319 if (unlikely(pl022->rx > pl022->rx_end)) { in pl022_interrupt_handler()
1320 dev_warn(&pl022->adev->dev, "read %u surplus " in pl022_interrupt_handler()
1323 (u32) (pl022->rx - pl022->rx_end)); in pl022_interrupt_handler()
1326 msg->actual_length += pl022->cur_transfer->len; in pl022_interrupt_handler()
1328 msg->state = next_transfer(pl022); in pl022_interrupt_handler()
1329 if (msg->state != STATE_DONE && pl022->cur_transfer->cs_change) in pl022_interrupt_handler()
1331 tasklet_schedule(&pl022->pump_transfers); in pl022_interrupt_handler()
1348 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; in set_up_next_transfer()
1350 dev_err(&pl022->adev->dev, in set_up_next_transfer()
1353 pl022->cur_transfer->len, in set_up_next_transfer()
1354 pl022->cur_chip->n_bytes); in set_up_next_transfer()
1355 dev_err(&pl022->adev->dev, "skipping this message\n"); in set_up_next_transfer()
1356 return -EIO; in set_up_next_transfer()
1358 pl022->tx = (void *)transfer->tx_buf; in set_up_next_transfer()
1359 pl022->tx_end = pl022->tx + pl022->cur_transfer->len; in set_up_next_transfer()
1360 pl022->rx = (void *)transfer->rx_buf; in set_up_next_transfer()
1361 pl022->rx_end = pl022->rx + pl022->cur_transfer->len; in set_up_next_transfer()
1362 pl022->write = in set_up_next_transfer()
1363 pl022->tx ? pl022->cur_chip->write : WRITING_NULL; in set_up_next_transfer()
1364 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; in set_up_next_transfer()
1369 * pump_transfers - Tasklet function which schedules next transfer
1382 message = pl022->cur_msg; in pump_transfers()
1383 transfer = pl022->cur_transfer; in pump_transfers()
1386 if (message->state == STATE_ERROR) { in pump_transfers()
1387 message->status = -EIO; in pump_transfers()
1393 if (message->state == STATE_DONE) { in pump_transfers()
1394 message->status = 0; in pump_transfers()
1400 if (message->state == STATE_RUNNING) { in pump_transfers()
1401 previous = list_entry(transfer->transfer_list.prev, in pump_transfers()
1404 if (previous->delay_usecs) in pump_transfers()
1409 udelay(previous->delay_usecs); in pump_transfers()
1412 if (previous->cs_change) in pump_transfers()
1416 message->state = STATE_RUNNING; in pump_transfers()
1420 message->state = STATE_ERROR; in pump_transfers()
1421 message->status = -EIO; in pump_transfers()
1428 if (pl022->cur_chip->enable_dma) { in pump_transfers()
1430 dev_dbg(&pl022->adev->dev, in pump_transfers()
1438 /* enable all interrupts except RX */ in pump_transfers()
1439 writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); in pump_transfers()
1445 * Default is to enable all interrupts except RX - in do_interrupt_dma_transfer()
1451 if (!pl022->next_msg_cs_active) in do_interrupt_dma_transfer()
1454 if (set_up_next_transfer(pl022, pl022->cur_transfer)) { in do_interrupt_dma_transfer()
1456 pl022->cur_msg->state = STATE_ERROR; in do_interrupt_dma_transfer()
1457 pl022->cur_msg->status = -EIO; in do_interrupt_dma_transfer()
1462 if (pl022->cur_chip->enable_dma) { in do_interrupt_dma_transfer()
1465 dev_dbg(&pl022->adev->dev, in do_interrupt_dma_transfer()
1474 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), in do_interrupt_dma_transfer()
1475 SSP_CR1(pl022->virtbase)); in do_interrupt_dma_transfer()
1476 writew(irqflags, SSP_IMSC(pl022->virtbase)); in do_interrupt_dma_transfer()
1484 if (pl022->vendor->extended_cr) in print_current_status()
1485 read_cr0 = readl(SSP_CR0(pl022->virtbase)); in print_current_status()
1487 read_cr0 = readw(SSP_CR0(pl022->virtbase)); in print_current_status()
1488 read_cr1 = readw(SSP_CR1(pl022->virtbase)); in print_current_status()
1489 read_dmacr = readw(SSP_DMACR(pl022->virtbase)); in print_current_status()
1490 read_sr = readw(SSP_SR(pl022->virtbase)); in print_current_status()
1492 dev_warn(&pl022->adev->dev, "spi-pl022 CR0: %x\n", read_cr0); in print_current_status()
1493 dev_warn(&pl022->adev->dev, "spi-pl022 CR1: %x\n", read_cr1); in print_current_status()
1494 dev_warn(&pl022->adev->dev, "spi-pl022 DMACR: %x\n", read_dmacr); in print_current_status()
1495 dev_warn(&pl022->adev->dev, "spi-pl022 SR: %x\n", read_sr); in print_current_status()
1496 dev_warn(&pl022->adev->dev, in print_current_status()
1497 "spi-pl022 exp_fifo_level/fifodepth: %u/%d\n", in print_current_status()
1498 pl022->exp_fifo_level, in print_current_status()
1499 pl022->vendor->fifodepth); in print_current_status()
1510 message = pl022->cur_msg; in do_polling_transfer()
1512 while (message->state != STATE_DONE) { in do_polling_transfer()
1514 if (message->state == STATE_ERROR) in do_polling_transfer()
1516 transfer = pl022->cur_transfer; in do_polling_transfer()
1519 if (message->state == STATE_RUNNING) { in do_polling_transfer()
1521 list_entry(transfer->transfer_list.prev, in do_polling_transfer()
1523 if (previous->delay_usecs) in do_polling_transfer()
1524 udelay(previous->delay_usecs); in do_polling_transfer()
1525 if (previous->cs_change) in do_polling_transfer()
1529 message->state = STATE_RUNNING; in do_polling_transfer()
1530 if (!pl022->next_msg_cs_active) in do_polling_transfer()
1537 message->state = STATE_ERROR; in do_polling_transfer()
1542 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), in do_polling_transfer()
1543 SSP_CR1(pl022->virtbase)); in do_polling_transfer()
1545 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); in do_polling_transfer()
1548 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { in do_polling_transfer()
1552 dev_warn(&pl022->adev->dev, in do_polling_transfer()
1554 message->state = STATE_TIMEOUT; in do_polling_transfer()
1562 message->actual_length += pl022->cur_transfer->len; in do_polling_transfer()
1564 message->state = next_transfer(pl022); in do_polling_transfer()
1565 if (message->state != STATE_DONE in do_polling_transfer()
1566 && pl022->cur_transfer->cs_change) in do_polling_transfer()
1571 if (message->state == STATE_DONE) in do_polling_transfer()
1572 message->status = 0; in do_polling_transfer()
1573 else if (message->state == STATE_TIMEOUT) in do_polling_transfer()
1574 message->status = -EAGAIN; in do_polling_transfer()
1576 message->status = -EIO; in do_polling_transfer()
1588 pl022->cur_msg = msg; in pl022_transfer_one_message()
1589 msg->state = STATE_START; in pl022_transfer_one_message()
1591 pl022->cur_transfer = list_entry(msg->transfers.next, in pl022_transfer_one_message()
1595 pl022->cur_chip = spi_get_ctldata(msg->spi); in pl022_transfer_one_message()
1596 pl022->cur_cs = pl022->chipselects[msg->spi->chip_select]; in pl022_transfer_one_message()
1601 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) in pl022_transfer_one_message()
1613 /* nothing more to do - disable spi/ssp and power off */ in pl022_unprepare_transfer_hardware()
1614 writew((readw(SSP_CR1(pl022->virtbase)) & in pl022_unprepare_transfer_hardware()
1615 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); in pl022_unprepare_transfer_hardware()
1623 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) in verify_controller_parameters()
1624 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { in verify_controller_parameters()
1625 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1627 return -EINVAL; in verify_controller_parameters()
1629 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && in verify_controller_parameters()
1630 (!pl022->vendor->unidir)) { in verify_controller_parameters()
1631 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1634 return -EINVAL; in verify_controller_parameters()
1636 if ((chip_info->hierarchy != SSP_MASTER) in verify_controller_parameters()
1637 && (chip_info->hierarchy != SSP_SLAVE)) { in verify_controller_parameters()
1638 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1640 return -EINVAL; in verify_controller_parameters()
1642 if ((chip_info->com_mode != INTERRUPT_TRANSFER) in verify_controller_parameters()
1643 && (chip_info->com_mode != DMA_TRANSFER) in verify_controller_parameters()
1644 && (chip_info->com_mode != POLLING_TRANSFER)) { in verify_controller_parameters()
1645 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1647 return -EINVAL; in verify_controller_parameters()
1649 switch (chip_info->rx_lev_trig) { in verify_controller_parameters()
1656 if (pl022->vendor->fifodepth < 16) { in verify_controller_parameters()
1657 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1658 "RX FIFO Trigger Level is configured incorrectly\n"); in verify_controller_parameters()
1659 return -EINVAL; in verify_controller_parameters()
1663 if (pl022->vendor->fifodepth < 32) { in verify_controller_parameters()
1664 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1665 "RX FIFO Trigger Level is configured incorrectly\n"); in verify_controller_parameters()
1666 return -EINVAL; in verify_controller_parameters()
1670 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1671 "RX FIFO Trigger Level is configured incorrectly\n"); in verify_controller_parameters()
1672 return -EINVAL; in verify_controller_parameters()
1674 switch (chip_info->tx_lev_trig) { in verify_controller_parameters()
1681 if (pl022->vendor->fifodepth < 16) { in verify_controller_parameters()
1682 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1683 "TX FIFO Trigger Level is configured incorrectly\n"); in verify_controller_parameters()
1684 return -EINVAL; in verify_controller_parameters()
1688 if (pl022->vendor->fifodepth < 32) { in verify_controller_parameters()
1689 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1690 "TX FIFO Trigger Level is configured incorrectly\n"); in verify_controller_parameters()
1691 return -EINVAL; in verify_controller_parameters()
1695 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1696 "TX FIFO Trigger Level is configured incorrectly\n"); in verify_controller_parameters()
1697 return -EINVAL; in verify_controller_parameters()
1699 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { in verify_controller_parameters()
1700 if ((chip_info->ctrl_len < SSP_BITS_4) in verify_controller_parameters()
1701 || (chip_info->ctrl_len > SSP_BITS_32)) { in verify_controller_parameters()
1702 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1704 return -EINVAL; in verify_controller_parameters()
1706 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) in verify_controller_parameters()
1707 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { in verify_controller_parameters()
1708 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1710 return -EINVAL; in verify_controller_parameters()
1713 if (pl022->vendor->extended_cr) { in verify_controller_parameters()
1714 if ((chip_info->duplex != in verify_controller_parameters()
1716 && (chip_info->duplex != in verify_controller_parameters()
1718 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1720 return -EINVAL; in verify_controller_parameters()
1723 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) in verify_controller_parameters()
1724 dev_err(&pl022->adev->dev, in verify_controller_parameters()
1728 return -EINVAL; in verify_controller_parameters()
1747 rate = clk_get_rate(pl022->clk); in calculate_effective_freq()
1754 dev_warn(&pl022->adev->dev, in calculate_effective_freq()
1759 dev_err(&pl022->adev->dev, in calculate_effective_freq()
1762 return -EINVAL; in calculate_effective_freq()
1804 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); in calculate_effective_freq()
1805 clk_freq->scr = (u8) (best_scr & 0xFF); in calculate_effective_freq()
1806 dev_dbg(&pl022->adev->dev, in calculate_effective_freq()
1809 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n", in calculate_effective_freq()
1810 clk_freq->cpsdvsr, clk_freq->scr); in calculate_effective_freq()
1833 * pl022_setup - setup function registered to SPI master framework
1851 struct pl022 *pl022 = spi_master_get_devdata(spi->master); in pl022_setup()
1852 unsigned int bits = spi->bits_per_word; in pl022_setup()
1854 struct device_node *np = spi->dev.of_node; in pl022_setup()
1856 if (!spi->max_speed_hz) in pl022_setup()
1857 return -EINVAL; in pl022_setup()
1865 return -ENOMEM; in pl022_setup()
1866 dev_dbg(&spi->dev, in pl022_setup()
1871 chip_info = spi->controller_data; in pl022_setup()
1880 of_property_read_u32(np, "pl022,com-mode", in pl022_setup()
1882 of_property_read_u32(np, "pl022,rx-level-trig", in pl022_setup()
1884 of_property_read_u32(np, "pl022,tx-level-trig", in pl022_setup()
1886 of_property_read_u32(np, "pl022,ctrl-len", in pl022_setup()
1888 of_property_read_u32(np, "pl022,wait-state", in pl022_setup()
1897 dev_dbg(&spi->dev, in pl022_setup()
1901 dev_dbg(&spi->dev, in pl022_setup()
1908 if ((0 == chip_info->clk_freq.cpsdvsr) in pl022_setup()
1909 && (0 == chip_info->clk_freq.scr)) { in pl022_setup()
1911 spi->max_speed_hz, in pl022_setup()
1916 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); in pl022_setup()
1919 clk_freq.cpsdvsr - 1; in pl022_setup()
1923 status = -EINVAL; in pl022_setup()
1924 dev_err(&spi->dev, in pl022_setup()
1931 dev_err(&spi->dev, "controller data is incorrect"); in pl022_setup()
1935 pl022->rx_lev_trig = chip_info->rx_lev_trig; in pl022_setup()
1936 pl022->tx_lev_trig = chip_info->tx_lev_trig; in pl022_setup()
1939 chip->xfer_type = chip_info->com_mode; in pl022_setup()
1940 if (!chip_info->cs_control) { in pl022_setup()
1941 chip->cs_control = null_cs_control; in pl022_setup()
1942 if (!gpio_is_valid(pl022->chipselects[spi->chip_select])) in pl022_setup()
1943 dev_warn(&spi->dev, in pl022_setup()
1946 chip->cs_control = chip_info->cs_control; in pl022_setup()
1949 if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) { in pl022_setup()
1950 status = -ENOTSUPP; in pl022_setup()
1951 dev_err(&spi->dev, "illegal data size for this controller!\n"); in pl022_setup()
1952 dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n", in pl022_setup()
1953 pl022->vendor->max_bpw); in pl022_setup()
1956 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); in pl022_setup()
1957 chip->n_bytes = 1; in pl022_setup()
1958 chip->read = READING_U8; in pl022_setup()
1959 chip->write = WRITING_U8; in pl022_setup()
1961 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); in pl022_setup()
1962 chip->n_bytes = 2; in pl022_setup()
1963 chip->read = READING_U16; in pl022_setup()
1964 chip->write = WRITING_U16; in pl022_setup()
1966 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); in pl022_setup()
1967 chip->n_bytes = 4; in pl022_setup()
1968 chip->read = READING_U32; in pl022_setup()
1969 chip->write = WRITING_U32; in pl022_setup()
1973 chip->cr0 = 0; in pl022_setup()
1974 chip->cr1 = 0; in pl022_setup()
1975 chip->dmacr = 0; in pl022_setup()
1976 chip->cpsr = 0; in pl022_setup()
1977 if ((chip_info->com_mode == DMA_TRANSFER) in pl022_setup()
1978 && ((pl022->master_info)->enable_dma)) { in pl022_setup()
1979 chip->enable_dma = true; in pl022_setup()
1980 dev_dbg(&spi->dev, "DMA mode set in controller state\n"); in pl022_setup()
1981 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, in pl022_setup()
1983 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, in pl022_setup()
1986 chip->enable_dma = false; in pl022_setup()
1987 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); in pl022_setup()
1988 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, in pl022_setup()
1990 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, in pl022_setup()
1994 chip->cpsr = clk_freq.cpsdvsr; in pl022_setup()
1997 if (pl022->vendor->extended_cr) { in pl022_setup()
2000 if (pl022->vendor->pl023) { in pl022_setup()
2002 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, in pl022_setup()
2006 SSP_WRITE_BITS(chip->cr0, chip_info->duplex, in pl022_setup()
2008 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, in pl022_setup()
2010 SSP_WRITE_BITS(chip->cr0, chip_info->iface, in pl022_setup()
2012 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, in pl022_setup()
2015 SSP_WRITE_BITS(chip->cr0, bits - 1, in pl022_setup()
2018 if (spi->mode & SPI_LSB_FIRST) { in pl022_setup()
2025 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); in pl022_setup()
2026 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); in pl022_setup()
2027 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, in pl022_setup()
2029 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, in pl022_setup()
2032 SSP_WRITE_BITS(chip->cr0, bits - 1, in pl022_setup()
2034 SSP_WRITE_BITS(chip->cr0, chip_info->iface, in pl022_setup()
2039 if (spi->mode & SPI_CPOL) in pl022_setup()
2043 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); in pl022_setup()
2045 if (spi->mode & SPI_CPHA) in pl022_setup()
2049 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); in pl022_setup()
2051 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); in pl022_setup()
2053 if (pl022->vendor->loopback) { in pl022_setup()
2054 if (spi->mode & SPI_LOOP) in pl022_setup()
2058 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); in pl022_setup()
2060 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); in pl022_setup()
2061 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); in pl022_setup()
2062 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, in pl022_setup()
2075 * pl022_cleanup - cleanup function registered to SPI master framework
2092 struct device_node *np = dev->of_node; in pl022_platform_data_dt_get()
2105 pd->bus_id = -1; in pl022_platform_data_dt_get()
2106 pd->enable_dma = 1; in pl022_platform_data_dt_get()
2107 of_property_read_u32(np, "num-cs", &tmp); in pl022_platform_data_dt_get()
2108 pd->num_chipselect = tmp; in pl022_platform_data_dt_get()
2109 of_property_read_u32(np, "pl022,autosuspend-delay", in pl022_platform_data_dt_get()
2110 &pd->autosuspend_delay); in pl022_platform_data_dt_get()
2111 pd->rt = of_property_read_bool(np, "pl022,rt"); in pl022_platform_data_dt_get()
2118 struct device *dev = &adev->dev; in pl022_probe()
2120 dev_get_platdata(&adev->dev); in pl022_probe()
2123 struct device_node *np = adev->dev.of_node; in pl022_probe()
2126 dev_info(&adev->dev, in pl022_probe()
2127 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); in pl022_probe()
2133 return -ENODEV; in pl022_probe()
2136 if (platform_info->num_chipselect) { in pl022_probe()
2137 num_cs = platform_info->num_chipselect; in pl022_probe()
2140 return -ENODEV; in pl022_probe()
2146 dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); in pl022_probe()
2147 return -ENOMEM; in pl022_probe()
2151 pl022->master = master; in pl022_probe()
2152 pl022->master_info = platform_info; in pl022_probe()
2153 pl022->adev = adev; in pl022_probe()
2154 pl022->vendor = id->data; in pl022_probe()
2155 pl022->chipselects = devm_kcalloc(dev, num_cs, sizeof(int), in pl022_probe()
2157 if (!pl022->chipselects) { in pl022_probe()
2158 status = -ENOMEM; in pl022_probe()
2166 master->bus_num = platform_info->bus_id; in pl022_probe()
2167 master->num_chipselect = num_cs; in pl022_probe()
2168 master->cleanup = pl022_cleanup; in pl022_probe()
2169 master->setup = pl022_setup; in pl022_probe()
2170 master->auto_runtime_pm = true; in pl022_probe()
2171 master->transfer_one_message = pl022_transfer_one_message; in pl022_probe()
2172 master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware; in pl022_probe()
2173 master->rt = platform_info->rt; in pl022_probe()
2174 master->dev.of_node = dev->of_node; in pl022_probe()
2176 if (platform_info->num_chipselect && platform_info->chipselects) { in pl022_probe()
2178 pl022->chipselects[i] = platform_info->chipselects[i]; in pl022_probe()
2179 } else if (pl022->vendor->internal_cs_ctrl) { in pl022_probe()
2181 pl022->chipselects[i] = i; in pl022_probe()
2184 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); in pl022_probe()
2186 if (cs_gpio == -EPROBE_DEFER) { in pl022_probe()
2187 status = -EPROBE_DEFER; in pl022_probe()
2191 pl022->chipselects[i] = cs_gpio; in pl022_probe()
2194 if (devm_gpio_request(dev, cs_gpio, "ssp-pl022")) in pl022_probe()
2195 dev_err(&adev->dev, in pl022_probe()
2199 dev_err(&adev->dev, in pl022_probe()
2207 * Supports mode 0-3, loopback, and active low CS. Transfers are in pl022_probe()
2210 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; in pl022_probe()
2211 if (pl022->vendor->extended_cr) in pl022_probe()
2212 master->mode_bits |= SPI_LSB_FIRST; in pl022_probe()
2214 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); in pl022_probe()
2220 pl022->phybase = adev->res.start; in pl022_probe()
2221 pl022->virtbase = devm_ioremap(dev, adev->res.start, in pl022_probe()
2222 resource_size(&adev->res)); in pl022_probe()
2223 if (pl022->virtbase == NULL) { in pl022_probe()
2224 status = -ENOMEM; in pl022_probe()
2227 dev_info(&adev->dev, "mapped registers from %pa to %p\n", in pl022_probe()
2228 &adev->res.start, pl022->virtbase); in pl022_probe()
2230 pl022->clk = devm_clk_get(&adev->dev, NULL); in pl022_probe()
2231 if (IS_ERR(pl022->clk)) { in pl022_probe()
2232 status = PTR_ERR(pl022->clk); in pl022_probe()
2233 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); in pl022_probe()
2237 status = clk_prepare_enable(pl022->clk); in pl022_probe()
2239 dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); in pl022_probe()
2244 tasklet_init(&pl022->pump_transfers, pump_transfers, in pl022_probe()
2248 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), in pl022_probe()
2249 SSP_CR1(pl022->virtbase)); in pl022_probe()
2252 status = devm_request_irq(dev, adev->irq[0], pl022_interrupt_handler, in pl022_probe()
2255 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); in pl022_probe()
2261 if (status == -EPROBE_DEFER) { in pl022_probe()
2268 platform_info->enable_dma = 1; in pl022_probe()
2269 else if (platform_info->enable_dma) { in pl022_probe()
2272 platform_info->enable_dma = 0; in pl022_probe()
2277 status = devm_spi_register_master(&adev->dev, master); in pl022_probe()
2279 dev_err(&adev->dev, in pl022_probe()
2280 "probe - problem registering spi master\n"); in pl022_probe()
2286 if (platform_info->autosuspend_delay > 0) { in pl022_probe()
2287 dev_info(&adev->dev, in pl022_probe()
2289 platform_info->autosuspend_delay); in pl022_probe()
2291 platform_info->autosuspend_delay); in pl022_probe()
2299 if (platform_info->enable_dma) in pl022_probe()
2302 clk_disable_unprepare(pl022->clk); in pl022_probe()
2326 pm_runtime_get_noresume(&adev->dev); in pl022_remove()
2329 if (pl022->master_info->enable_dma) in pl022_remove()
2332 clk_disable_unprepare(pl022->clk); in pl022_remove()
2334 tasklet_disable(&pl022->pump_transfers); in pl022_remove()
2344 ret = spi_master_suspend(pl022->master); in pl022_suspend()
2350 spi_master_resume(pl022->master); in pl022_suspend()
2370 ret = spi_master_resume(pl022->master); in pl022_resume()
2383 clk_disable_unprepare(pl022->clk); in pl022_runtime_suspend()
2394 clk_prepare_enable(pl022->clk); in pl022_runtime_resume()
2449 * and 8 locations deep TX/RX FIFO
2458 * and 32 locations deep TX/RX FIFO
2466 * ST-Ericsson derivative "PL023" (this is not
2469 * and 32 locations deep TX/RX FIFO but no extended
2492 .name = "ssp-pl022",