20 #include <linux/spi/spi.h>
189 static u32 lantiq_ssc_readl(const struct lantiq_ssc_spi *spi, u32 reg)  in lantiq_ssc_readl()  argument
191 	return __raw_readl(spi->regbase + reg);  in lantiq_ssc_readl()
194 static void lantiq_ssc_writel(const struct lantiq_ssc_spi *spi, u32 val,  in lantiq_ssc_writel()  argument
197 	__raw_writel(val, spi->regbase + reg);  in lantiq_ssc_writel()
200 static void lantiq_ssc_maskl(const struct lantiq_ssc_spi *spi, u32 clr,  in lantiq_ssc_maskl()  argument
203 	u32 val = __raw_readl(spi->regbase + reg);  in lantiq_ssc_maskl()
207 	__raw_writel(val, spi->regbase + reg);  in lantiq_ssc_maskl()
210 static unsigned int tx_fifo_level(const struct lantiq_ssc_spi *spi)  in tx_fifo_level()  argument
212 	u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT);  in tx_fifo_level()
217 static unsigned int rx_fifo_level(const struct lantiq_ssc_spi *spi)  in rx_fifo_level()  argument
219 	u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT);  in rx_fifo_level()
224 static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi)  in tx_fifo_free()  argument
226 	return spi->tx_fifo_size - tx_fifo_level(spi);  in tx_fifo_free()
229 static void rx_fifo_reset(const struct lantiq_ssc_spi *spi)  in rx_fifo_reset()  argument
231 	u32 val = spi->rx_fifo_size << LTQ_SPI_RXFCON_RXFITL_S;  in rx_fifo_reset()
234 	lantiq_ssc_writel(spi, val, LTQ_SPI_RXFCON);  in rx_fifo_reset()
237 static void tx_fifo_reset(const struct lantiq_ssc_spi *spi)  in tx_fifo_reset()  argument
242 	lantiq_ssc_writel(spi, val, LTQ_SPI_TXFCON);  in tx_fifo_reset()
245 static void rx_fifo_flush(const struct lantiq_ssc_spi *spi)  in rx_fifo_flush()  argument
247 	lantiq_ssc_maskl(spi, 0, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON);  in rx_fifo_flush()
250 static void tx_fifo_flush(const struct lantiq_ssc_spi *spi)  in tx_fifo_flush()  argument
252 	lantiq_ssc_maskl(spi, 0, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON);  in tx_fifo_flush()
255 static void hw_enter_config_mode(const struct lantiq_ssc_spi *spi)  in hw_enter_config_mode()  argument
257 	lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE);  in hw_enter_config_mode()
260 static void hw_enter_active_mode(const struct lantiq_ssc_spi *spi)  in hw_enter_active_mode()  argument
262 	lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE);  in hw_enter_active_mode()
265 static void hw_setup_speed_hz(const struct lantiq_ssc_spi *spi,  in hw_setup_speed_hz()  argument
271 	 * SPI module clock is derived from FPI bus clock dependent on  in hw_setup_speed_hz()
278 	spi_clk = clk_get_rate(spi->fpi_clk) / 2;  in hw_setup_speed_hz()
288 	dev_dbg(spi->dev, "spi_clk %u, max_speed_hz %u, brt %u\n",  in hw_setup_speed_hz()
291 	lantiq_ssc_writel(spi, brt, LTQ_SPI_BRT);  in hw_setup_speed_hz()
294 static void hw_setup_bits_per_word(const struct lantiq_ssc_spi *spi,  in hw_setup_bits_per_word()  argument
302 	lantiq_ssc_maskl(spi, LTQ_SPI_CON_BM_M, bm, LTQ_SPI_CON);  in hw_setup_bits_per_word()
305 static void hw_setup_clock_mode(const struct lantiq_ssc_spi *spi,  in hw_setup_clock_mode()  argument
311 	 * SPI mode mapping in CON register:  in hw_setup_clock_mode()
340 	lantiq_ssc_maskl(spi, con_clr, con_set, LTQ_SPI_CON);  in hw_setup_clock_mode()
343 static void lantiq_ssc_hw_init(const struct lantiq_ssc_spi *spi)  in lantiq_ssc_hw_init()  argument
345 	const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;  in lantiq_ssc_hw_init()
351 	lantiq_ssc_writel(spi, 1 << LTQ_SPI_CLC_RMC_S, LTQ_SPI_CLC);  in lantiq_ssc_hw_init()
354 	hw_enter_config_mode(spi);  in lantiq_ssc_hw_init()
357 	lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);  in lantiq_ssc_hw_init()
360 	lantiq_ssc_writel(spi, LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN |  in lantiq_ssc_hw_init()
364 	/* Setup default SPI mode */  in lantiq_ssc_hw_init()
365 	hw_setup_bits_per_word(spi, spi->bits_per_word);  in lantiq_ssc_hw_init()
366 	hw_setup_clock_mode(spi, SPI_MODE_0);  in lantiq_ssc_hw_init()
369 	lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETMS |  in lantiq_ssc_hw_init()
374 	lantiq_ssc_writel(spi, 0, LTQ_SPI_GPOCON);  in lantiq_ssc_hw_init()
375 	lantiq_ssc_writel(spi, 0xFF00, LTQ_SPI_FPGO);  in lantiq_ssc_hw_init()
378 	rx_fifo_reset(spi);  in lantiq_ssc_hw_init()
379 	tx_fifo_reset(spi);  in lantiq_ssc_hw_init()
382 	lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r |  in lantiq_ssc_hw_init()
389 	struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);  in lantiq_ssc_setup()  local
397 	dev_dbg(spi->dev, "using internal chipselect %u\n", cs);  in lantiq_ssc_setup()
399 	if (cs < spi->base_cs) {  in lantiq_ssc_setup()
400 		dev_err(spi->dev,  in lantiq_ssc_setup()
401 			"chipselect %i too small (min %i)\n", cs, spi->base_cs);  in lantiq_ssc_setup()
406 	gpocon = 1 << ((cs - spi->base_cs) + LTQ_SPI_GPOCON_ISCSBN_S);  in lantiq_ssc_setup()
410 		gpocon |= 1 << (cs - spi->base_cs);  in lantiq_ssc_setup()
412 	lantiq_ssc_maskl(spi, 0, gpocon, LTQ_SPI_GPOCON);  in lantiq_ssc_setup()
420 	struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);  in lantiq_ssc_prepare_message()  local
422 	hw_enter_config_mode(spi);  in lantiq_ssc_prepare_message()
423 	hw_setup_clock_mode(spi, message->spi->mode);  in lantiq_ssc_prepare_message()
424 	hw_enter_active_mode(spi);  in lantiq_ssc_prepare_message()
429 static void hw_setup_transfer(struct lantiq_ssc_spi *spi,  in hw_setup_transfer()  argument
436 	if (bits_per_word != spi->bits_per_word ||  in hw_setup_transfer()
437 		speed_hz != spi->speed_hz) {  in hw_setup_transfer()
438 		hw_enter_config_mode(spi);  in hw_setup_transfer()
439 		hw_setup_speed_hz(spi, speed_hz);  in hw_setup_transfer()
440 		hw_setup_bits_per_word(spi, bits_per_word);  in hw_setup_transfer()
441 		hw_enter_active_mode(spi);  in hw_setup_transfer()
443 		spi->speed_hz = speed_hz;  in hw_setup_transfer()
444 		spi->bits_per_word = bits_per_word;  in hw_setup_transfer()
448 	con = lantiq_ssc_readl(spi, LTQ_SPI_CON);  in hw_setup_transfer()
459 	lantiq_ssc_writel(spi, con, LTQ_SPI_CON);  in hw_setup_transfer()
465 	struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);  in lantiq_ssc_unprepare_message()  local
467 	flush_workqueue(spi->wq);  in lantiq_ssc_unprepare_message()
470 	lantiq_ssc_maskl(spi, 0, LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF,  in lantiq_ssc_unprepare_message()
476 static void tx_fifo_write(struct lantiq_ssc_spi *spi)  in tx_fifo_write()  argument
482 	unsigned int tx_free = tx_fifo_free(spi);  in tx_fifo_write()
484 	while (spi->tx_todo && tx_free) {  in tx_fifo_write()
485 		switch (spi->bits_per_word) {  in tx_fifo_write()
487 			tx8 = spi->tx;  in tx_fifo_write()
489 			spi->tx_todo--;  in tx_fifo_write()
490 			spi->tx++;  in tx_fifo_write()
493 			tx16 = (u16 *) spi->tx;  in tx_fifo_write()
495 			spi->tx_todo -= 2;  in tx_fifo_write()
496 			spi->tx += 2;  in tx_fifo_write()
499 			tx32 = (u32 *) spi->tx;  in tx_fifo_write()
501 			spi->tx_todo -= 4;  in tx_fifo_write()
502 			spi->tx += 4;  in tx_fifo_write()
510 		lantiq_ssc_writel(spi, data, LTQ_SPI_TB);  in tx_fifo_write()
515 static void rx_fifo_read_full_duplex(struct lantiq_ssc_spi *spi)  in rx_fifo_read_full_duplex()  argument
521 	unsigned int rx_fill = rx_fifo_level(spi);  in rx_fifo_read_full_duplex()
524 		data = lantiq_ssc_readl(spi, LTQ_SPI_RB);  in rx_fifo_read_full_duplex()
526 		switch (spi->bits_per_word) {  in rx_fifo_read_full_duplex()
528 			rx8 = spi->rx;  in rx_fifo_read_full_duplex()
530 			spi->rx_todo--;  in rx_fifo_read_full_duplex()
531 			spi->rx++;  in rx_fifo_read_full_duplex()
534 			rx16 = (u16 *) spi->rx;  in rx_fifo_read_full_duplex()
536 			spi->rx_todo -= 2;  in rx_fifo_read_full_duplex()
537 			spi->rx += 2;  in rx_fifo_read_full_duplex()
540 			rx32 = (u32 *) spi->rx;  in rx_fifo_read_full_duplex()
542 			spi->rx_todo -= 4;  in rx_fifo_read_full_duplex()
543 			spi->rx += 4;  in rx_fifo_read_full_duplex()
554 static void rx_fifo_read_half_duplex(struct lantiq_ssc_spi *spi)  in rx_fifo_read_half_duplex()  argument
559 	unsigned int rx_fill = rx_fifo_level(spi);  in rx_fifo_read_half_duplex()
569 		if (spi->rx_todo < 4)  {  in rx_fifo_read_half_duplex()
570 			rxbv = (lantiq_ssc_readl(spi, LTQ_SPI_STAT) &  in rx_fifo_read_half_duplex()
572 			data = lantiq_ssc_readl(spi, LTQ_SPI_RB);  in rx_fifo_read_half_duplex()
575 			rx8 = spi->rx;  in rx_fifo_read_half_duplex()
581 				spi->rx_todo--;  in rx_fifo_read_half_duplex()
582 				spi->rx++;  in rx_fifo_read_half_duplex()
585 			data = lantiq_ssc_readl(spi, LTQ_SPI_RB);  in rx_fifo_read_half_duplex()
586 			rx32 = (u32 *) spi->rx;  in rx_fifo_read_half_duplex()
589 			spi->rx_todo -= 4;  in rx_fifo_read_half_duplex()
590 			spi->rx += 4;  in rx_fifo_read_half_duplex()
596 static void rx_request(struct lantiq_ssc_spi *spi)  in rx_request()  argument
605 	rxreq = spi->rx_todo;  in rx_request()
606 	rxreq_max = spi->rx_fifo_size * 4;  in rx_request()
610 	lantiq_ssc_writel(spi, rxreq, LTQ_SPI_RXREQ);  in rx_request()
615 	struct lantiq_ssc_spi *spi = data;  in lantiq_ssc_xmit_interrupt()  local
617 	if (spi->tx) {  in lantiq_ssc_xmit_interrupt()
618 		if (spi->rx && spi->rx_todo)  in lantiq_ssc_xmit_interrupt()
619 			rx_fifo_read_full_duplex(spi);  in lantiq_ssc_xmit_interrupt()
621 		if (spi->tx_todo)  in lantiq_ssc_xmit_interrupt()
622 			tx_fifo_write(spi);  in lantiq_ssc_xmit_interrupt()
623 		else if (!tx_fifo_level(spi))  in lantiq_ssc_xmit_interrupt()
625 	} else if (spi->rx) {  in lantiq_ssc_xmit_interrupt()
626 		if (spi->rx_todo) {  in lantiq_ssc_xmit_interrupt()
627 			rx_fifo_read_half_duplex(spi);  in lantiq_ssc_xmit_interrupt()
629 			if (spi->rx_todo)  in lantiq_ssc_xmit_interrupt()
630 				rx_request(spi);  in lantiq_ssc_xmit_interrupt()
641 	queue_work(spi->wq, &spi->work);  in lantiq_ssc_xmit_interrupt()
648 	struct lantiq_ssc_spi *spi = data;  in lantiq_ssc_err_interrupt()  local
649 	u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT);  in lantiq_ssc_err_interrupt()
655 		dev_err(spi->dev, "receive underflow error\n");  in lantiq_ssc_err_interrupt()
657 		dev_err(spi->dev, "transmit underflow error\n");  in lantiq_ssc_err_interrupt()
659 		dev_err(spi->dev, "abort error\n");  in lantiq_ssc_err_interrupt()
661 		dev_err(spi->dev, "receive overflow error\n");  in lantiq_ssc_err_interrupt()
663 		dev_err(spi->dev, "transmit overflow error\n");  in lantiq_ssc_err_interrupt()
665 		dev_err(spi->dev, "mode error\n");  in lantiq_ssc_err_interrupt()
668 	lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);  in lantiq_ssc_err_interrupt()
671 	if (spi->master->cur_msg)  in lantiq_ssc_err_interrupt()
672 		spi->master->cur_msg->status = -EIO;  in lantiq_ssc_err_interrupt()
673 	queue_work(spi->wq, &spi->work);  in lantiq_ssc_err_interrupt()
678 static int transfer_start(struct lantiq_ssc_spi *spi, struct spi_device *spidev,  in transfer_start()  argument
683 	spin_lock_irqsave(&spi->lock, flags);  in transfer_start()
685 	spi->tx = t->tx_buf;  in transfer_start()
686 	spi->rx = t->rx_buf;  in transfer_start()
689 		spi->tx_todo = t->len;  in transfer_start()
692 		tx_fifo_write(spi);  in transfer_start()
695 	if (spi->rx) {  in transfer_start()
696 		spi->rx_todo = t->len;  in transfer_start()
699 		if (!spi->tx)  in transfer_start()
700 			rx_request(spi);  in transfer_start()
703 	spin_unlock_irqrestore(&spi->lock, flags);  in transfer_start()
717 	struct lantiq_ssc_spi *spi;  in lantiq_ssc_bussy_work()  local
721 	spi = container_of(work, typeof(*spi), work);  in lantiq_ssc_bussy_work()
723 	do_div(timeout, spi->speed_hz);  in lantiq_ssc_bussy_work()
728 		u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT);  in lantiq_ssc_bussy_work()
731 			spi_finalize_current_transfer(spi->master);  in lantiq_ssc_bussy_work()
738 	if (spi->master->cur_msg)  in lantiq_ssc_bussy_work()
739 		spi->master->cur_msg->status = -EIO;  in lantiq_ssc_bussy_work()
740 	spi_finalize_current_transfer(spi->master);  in lantiq_ssc_bussy_work()
746 	struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);  in lantiq_ssc_handle_err()  local
749 	rx_fifo_flush(spi);  in lantiq_ssc_handle_err()
750 	tx_fifo_flush(spi);  in lantiq_ssc_handle_err()
755 	struct lantiq_ssc_spi *spi = spi_master_get_devdata(spidev->master);  in lantiq_ssc_set_cs()  local
760 		fgpo = (1 << (cs - spi->base_cs));  in lantiq_ssc_set_cs()
762 		fgpo = (1 << (cs - spi->base_cs + LTQ_SPI_FGPO_SETOUTN_S));  in lantiq_ssc_set_cs()
764 	lantiq_ssc_writel(spi, fgpo, LTQ_SPI_FPGO);  in lantiq_ssc_set_cs()
771 	struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);  in lantiq_ssc_transfer_one()  local
773 	hw_setup_transfer(spi, spidev, t);  in lantiq_ssc_transfer_one()
775 	return transfer_start(spi, spidev, t);  in lantiq_ssc_transfer_one()
789 	{ .compatible = "lantiq,ase-spi", .data = &lantiq_ssc_xway, },
790 	{ .compatible = "lantiq,falcon-spi", .data = &lantiq_ssc_xrx, },
791 	{ .compatible = "lantiq,xrx100-spi", .data = &lantiq_ssc_xrx, },
801 	struct lantiq_ssc_spi *spi;  in lantiq_ssc_probe()  local
837 	spi = spi_master_get_devdata(master);  in lantiq_ssc_probe()
838 	spi->master = master;  in lantiq_ssc_probe()
839 	spi->dev = dev;  in lantiq_ssc_probe()
840 	spi->hwcfg = hwcfg;  in lantiq_ssc_probe()
841 	platform_set_drvdata(pdev, spi);  in lantiq_ssc_probe()
843 	spi->regbase = devm_ioremap_resource(dev, res);  in lantiq_ssc_probe()
844 	if (IS_ERR(spi->regbase)) {  in lantiq_ssc_probe()
845 		err = PTR_ERR(spi->regbase);  in lantiq_ssc_probe()
850 			       0, LTQ_SPI_RX_IRQ_NAME, spi);  in lantiq_ssc_probe()
855 			       0, LTQ_SPI_TX_IRQ_NAME, spi);  in lantiq_ssc_probe()
860 			       0, LTQ_SPI_ERR_IRQ_NAME, spi);  in lantiq_ssc_probe()
864 	spi->spi_clk = devm_clk_get(dev, "gate");  in lantiq_ssc_probe()
865 	if (IS_ERR(spi->spi_clk)) {  in lantiq_ssc_probe()
866 		err = PTR_ERR(spi->spi_clk);  in lantiq_ssc_probe()
869 	err = clk_prepare_enable(spi->spi_clk);  in lantiq_ssc_probe()
878 	spi->fpi_clk = clk_get_fpi();  in lantiq_ssc_probe()
880 	spi->fpi_clk = clk_get(dev, "freq");  in lantiq_ssc_probe()
882 	if (IS_ERR(spi->fpi_clk)) {  in lantiq_ssc_probe()
883 		err = PTR_ERR(spi->fpi_clk);  in lantiq_ssc_probe()
890 	spi->base_cs = 1;  in lantiq_ssc_probe()
891 	of_property_read_u32(pdev->dev.of_node, "base-cs", &spi->base_cs);  in lantiq_ssc_probe()
893 	spin_lock_init(&spi->lock);  in lantiq_ssc_probe()
894 	spi->bits_per_word = 8;  in lantiq_ssc_probe()
895 	spi->speed_hz = 0;  in lantiq_ssc_probe()
910 	spi->wq = alloc_ordered_workqueue(dev_name(dev), 0);  in lantiq_ssc_probe()
911 	if (!spi->wq) {  in lantiq_ssc_probe()
915 	INIT_WORK(&spi->work, lantiq_ssc_bussy_work);  in lantiq_ssc_probe()
917 	id = lantiq_ssc_readl(spi, LTQ_SPI_ID);  in lantiq_ssc_probe()
918 	spi->tx_fifo_size = (id & LTQ_SPI_ID_TXFS_M) >> LTQ_SPI_ID_TXFS_S;  in lantiq_ssc_probe()
919 	spi->rx_fifo_size = (id & LTQ_SPI_ID_RXFS_M) >> LTQ_SPI_ID_RXFS_S;  in lantiq_ssc_probe()
923 	lantiq_ssc_hw_init(spi);  in lantiq_ssc_probe()
926 		"Lantiq SSC SPI controller (Rev %i, TXFS %u, RXFS %u, DMA %u)\n",  in lantiq_ssc_probe()
927 		revision, spi->tx_fifo_size, spi->rx_fifo_size, supports_dma);  in lantiq_ssc_probe()
938 	destroy_workqueue(spi->wq);  in lantiq_ssc_probe()
940 	clk_put(spi->fpi_clk);  in lantiq_ssc_probe()
942 	clk_disable_unprepare(spi->spi_clk);  in lantiq_ssc_probe()
951 	struct lantiq_ssc_spi *spi = platform_get_drvdata(pdev);  in lantiq_ssc_remove()  local
953 	lantiq_ssc_writel(spi, 0, LTQ_SPI_IRNEN);  in lantiq_ssc_remove()
954 	lantiq_ssc_writel(spi, 0, LTQ_SPI_CLC);  in lantiq_ssc_remove()
955 	rx_fifo_flush(spi);  in lantiq_ssc_remove()
956 	tx_fifo_flush(spi);  in lantiq_ssc_remove()
957 	hw_enter_config_mode(spi);  in lantiq_ssc_remove()
959 	destroy_workqueue(spi->wq);  in lantiq_ssc_remove()
960 	clk_disable_unprepare(spi->spi_clk);  in lantiq_ssc_remove()
961 	clk_put(spi->fpi_clk);  in lantiq_ssc_remove()
970 		.name = "spi-lantiq-ssc",
976 MODULE_DESCRIPTION("Lantiq SSC SPI controller driver");
980 MODULE_ALIAS("platform:spi-lantiq-ssc");