93 	struct fsl_spi_reg *reg_base = mspi->reg_base;  in fsl_spi_change_mode()  local
94 	__be32 __iomem *mode = &reg_base->mode;  in fsl_spi_change_mode()
294 	struct fsl_spi_reg *reg_base = mspi->reg_base;  in fsl_spi_cpu_bufs()  local
299 	mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);  in fsl_spi_cpu_bufs()
303 	mpc8xxx_spi_write_reg(&reg_base->transmit, word);  in fsl_spi_cpu_bufs()
312 	struct fsl_spi_reg *reg_base;  in fsl_spi_bufs()  local
317 	reg_base = mpc8xxx_spi->reg_base;  in fsl_spi_bufs()
350 	mpc8xxx_spi_write_reg(&reg_base->mask, 0);  in fsl_spi_bufs()
444 	struct fsl_spi_reg *reg_base;  in fsl_spi_setup()  local
460 	reg_base = mpc8xxx_spi->reg_base;  in fsl_spi_setup()
463 	cs->hw_mode = mpc8xxx_spi_read_reg(&reg_base->mode);  in fsl_spi_setup()
499 	struct fsl_spi_reg *reg_base = mspi->reg_base;  in fsl_spi_cpu_irq()  local
503 		u32 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);  in fsl_spi_cpu_irq()
512 			mpc8xxx_spi_read_reg(&reg_base->event)) &  in fsl_spi_cpu_irq()
517 	mpc8xxx_spi_write_reg(&reg_base->event, events);  in fsl_spi_cpu_irq()
523 		mpc8xxx_spi_write_reg(&reg_base->transmit, word);  in fsl_spi_cpu_irq()
534 	struct fsl_spi_reg *reg_base = mspi->reg_base;  in fsl_spi_irq()  local
537 	events = mpc8xxx_spi_read_reg(&reg_base->event);  in fsl_spi_irq()
554 	struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;  in fsl_spi_grlib_cs_control()  local
561 		slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel);  in fsl_spi_grlib_cs_control()
563 		mpc8xxx_spi_write_reg(&reg_base->slvsel, slvsel);  in fsl_spi_grlib_cs_control()
572 	struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;  in fsl_spi_grlib_probe()  local
576 	capabilities = mpc8xxx_spi_read_reg(&reg_base->cap);  in fsl_spi_grlib_probe()
586 		mpc8xxx_spi_write_reg(&reg_base->slvsel, 0xffffffff);  in fsl_spi_grlib_probe()
598 	struct fsl_spi_reg *reg_base;  in fsl_spi_probe()  local
624 	mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);  in fsl_spi_probe()
625 	if (IS_ERR(mpc8xxx_spi->reg_base)) {  in fsl_spi_probe()
626 		ret = PTR_ERR(mpc8xxx_spi->reg_base);  in fsl_spi_probe()
652 	reg_base = mpc8xxx_spi->reg_base;  in fsl_spi_probe()
655 	mpc8xxx_spi_write_reg(&reg_base->mode, 0);  in fsl_spi_probe()
656 	mpc8xxx_spi_write_reg(&reg_base->mask, 0);  in fsl_spi_probe()
657 	mpc8xxx_spi_write_reg(&reg_base->command, 0);  in fsl_spi_probe()
658 	mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);  in fsl_spi_probe()
669 	mpc8xxx_spi_write_reg(&reg_base->mode, regval);  in fsl_spi_probe()
675 	dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,  in fsl_spi_probe()