94 	int (*dma_init)(struct dw_spi *dws);
95 	void (*dma_exit)(struct dw_spi *dws);
96 	int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
99 	int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
100 	void (*dma_stop)(struct dw_spi *dws);
128 	irqreturn_t		(*transfer_handler)(struct dw_spi *dws);
148 static inline u32 dw_readl(struct dw_spi *dws, u32 offset)  in dw_readl()  argument
150 	return __raw_readl(dws->regs + offset);  in dw_readl()
153 static inline u16 dw_readw(struct dw_spi *dws, u32 offset)  in dw_readw()  argument
155 	return __raw_readw(dws->regs + offset);  in dw_readw()
158 static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)  in dw_writel()  argument
160 	__raw_writel(val, dws->regs + offset);  in dw_writel()
163 static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val)  in dw_writew()  argument
165 	__raw_writew(val, dws->regs + offset);  in dw_writew()
168 static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)  in dw_read_io_reg()  argument
170 	switch (dws->reg_io_width) {  in dw_read_io_reg()
172 		return dw_readw(dws, offset);  in dw_read_io_reg()
175 		return dw_readl(dws, offset);  in dw_read_io_reg()
179 static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)  in dw_write_io_reg()  argument
181 	switch (dws->reg_io_width) {  in dw_write_io_reg()
183 		dw_writew(dws, offset, val);  in dw_write_io_reg()
187 		dw_writel(dws, offset, val);  in dw_write_io_reg()
192 static inline void spi_enable_chip(struct dw_spi *dws, int enable)  in spi_enable_chip()  argument
194 	dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));  in spi_enable_chip()
197 static inline void spi_set_clk(struct dw_spi *dws, u16 div)  in spi_set_clk()  argument
199 	dw_writel(dws, DW_SPI_BAUDR, div);  in spi_set_clk()
203 static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)  in spi_mask_intr()  argument
207 	new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;  in spi_mask_intr()
208 	dw_writel(dws, DW_SPI_IMR, new_mask);  in spi_mask_intr()
212 static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)  in spi_umask_intr()  argument
216 	new_mask = dw_readl(dws, DW_SPI_IMR) | mask;  in spi_umask_intr()
217 	dw_writel(dws, DW_SPI_IMR, new_mask);  in spi_umask_intr()
225 static inline void spi_reset_chip(struct dw_spi *dws)  in spi_reset_chip()  argument
227 	spi_enable_chip(dws, 0);  in spi_reset_chip()
228 	spi_mask_intr(dws, 0xff);  in spi_reset_chip()
229 	spi_enable_chip(dws, 1);  in spi_reset_chip()
232 static inline void spi_shutdown_chip(struct dw_spi *dws)  in spi_shutdown_chip()  argument
234 	spi_enable_chip(dws, 0);  in spi_shutdown_chip()
235 	spi_set_clk(dws, 0);  in spi_shutdown_chip()
251 extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
252 extern void dw_spi_remove_host(struct dw_spi *dws);
253 extern int dw_spi_suspend_host(struct dw_spi *dws);
254 extern int dw_spi_resume_host(struct dw_spi *dws);
257 extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */