313 	int sync_reg, ret;  in intel_shim_init()  local
352 	sync_reg = intel_readl(shim, SDW_SHIM_SYNC);  in intel_shim_init()
353 	sync_reg |= (SDW_SHIM_SYNC_SYNCPRD_VAL <<  in intel_shim_init()
357 	sync_reg |= SDW_SHIM_SYNC_SYNCCPU;  in intel_shim_init()
358 	ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,  in intel_shim_init()
548 	int sync_reg;  in intel_pre_bank_switch()  local
555 	sync_reg = intel_readl(shim, SDW_SHIM_SYNC);  in intel_pre_bank_switch()
556 	sync_reg |= SDW_SHIM_SYNC_CMDSYNC << sdw->instance;  in intel_pre_bank_switch()
557 	intel_writel(shim, SDW_SHIM_SYNC, sync_reg);  in intel_pre_bank_switch()
567 	int sync_reg, ret;  in intel_post_bank_switch()  local
574 	sync_reg = intel_readl(shim, SDW_SHIM_SYNC);  in intel_post_bank_switch()
584 	if (!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK))  in intel_post_bank_switch()
592 	sync_reg |= SDW_SHIM_SYNC_SYNCGO;  in intel_post_bank_switch()
594 	ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,  in intel_post_bank_switch()