Lines Matching refs:uint16_t
116 uint16_t id_l; /* ID low */
117 uint16_t id_h; /* ID high */
118 uint16_t cfg_0; /* Configuration 0 */
126 uint16_t cfg_1; /* Configuration 1 */
133 uint16_t ictrl; /* Interface control */
139 uint16_t istatus; /* Interface status */
143 uint16_t semaphore; /* Semaphore */
144 uint16_t nvram; /* NVRAM register. */
150 uint16_t flash_data; /* Flash BIOS data */
151 uint16_t flash_address; /* Flash BIOS address */
153 uint16_t unused_1[0x06];
156 uint16_t cdma_cfg;
161 uint16_t cdma_ctrl;
162 uint16_t cdma_status;
163 uint16_t cdma_fifo_status;
164 uint16_t cdma_count;
165 uint16_t cdma_reserved;
166 uint16_t cdma_address_count_0;
167 uint16_t cdma_address_count_1;
168 uint16_t cdma_address_count_2;
169 uint16_t cdma_address_count_3;
171 uint16_t unused_2[0x06];
173 uint16_t ddma_cfg;
178 uint16_t ddma_ctrl;
179 uint16_t ddma_status;
180 uint16_t ddma_fifo_status;
181 uint16_t ddma_xfer_count_low;
182 uint16_t ddma_xfer_count_high;
183 uint16_t ddma_addr_count_0;
184 uint16_t ddma_addr_count_1;
185 uint16_t ddma_addr_count_2;
186 uint16_t ddma_addr_count_3;
188 uint16_t unused_3[0x0e];
190 uint16_t mailbox0; /* Mailbox 0 */
191 uint16_t mailbox1; /* Mailbox 1 */
192 uint16_t mailbox2; /* Mailbox 2 */
193 uint16_t mailbox3; /* Mailbox 3 */
194 uint16_t mailbox4; /* Mailbox 4 */
195 uint16_t mailbox5; /* Mailbox 5 */
196 uint16_t mailbox6; /* Mailbox 6 */
197 uint16_t mailbox7; /* Mailbox 7 */
199 uint16_t unused_4[0x20];/* 0x80-0xbf Gap */
201 uint16_t host_cmd; /* Host command and control */
205 uint16_t unused_5[0x5]; /* 0xc2-0xcb Gap */
207 uint16_t gpio_data;
208 uint16_t gpio_enable;
210 uint16_t unused_6[0x11]; /* d0-f0 */
211 uint16_t scsiControlPins; /* f2 */
365 uint16_t unused_8; /* 8, 9 */
366 uint16_t unused_10; /* 10, 11 */
367 uint16_t unused_12; /* 12, 13 */
368 uint16_t unused_14; /* 14, 15 */
389 uint16_t isp_parameter; /* 18, 19 */
392 uint16_t w;
394 uint16_t enable_fast_posting:1;
395 uint16_t report_lvd_bus_transition:1;
396 uint16_t unused_2:1;
397 uint16_t unused_3:1;
398 uint16_t disable_iosbs_with_bus_reset_status:1;
399 uint16_t disable_synchronous_backoff:1;
400 uint16_t unused_6:1;
401 uint16_t synchronous_backoff_reporting:1;
402 uint16_t disable_reselection_fairness:1;
403 uint16_t unused_9:1;
404 uint16_t unused_10:1;
405 uint16_t unused_11:1;
406 uint16_t unused_12:1;
407 uint16_t unused_13:1;
408 uint16_t unused_14:1;
409 uint16_t unused_15:1;
413 uint16_t unused_22; /* 22, 23 */
438 uint16_t selection_timeout; /* 30, 31 */
439 uint16_t max_queue_depth; /* 32, 33 */
441 uint16_t unused_34; /* 34, 35 */
442 uint16_t unused_36; /* 36, 37 */
443 uint16_t unused_38; /* 38, 39 */
489 uint16_t unused_248; /* 248, 249 */
491 uint16_t subsystem_id[2]; /* 250, 251, 252, 253 */
985 uint16_t device_enables; /* Device enable bits. */
986 uint16_t lun_disables; /* LUN disable bits. */
987 uint16_t qtag_enables; /* Tag queue enables. */
988 uint16_t hiwat; /* High water mark per device. */
1000 uint16_t sync_mask;
1001 uint16_t wide_mask;
1002 uint16_t ppr_mask;
1033 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
1038 uint16_t req_ring_index; /* Current index. */
1039 uint16_t req_q_cnt; /* Number of available entries. */
1044 uint16_t rsp_ring_index; /* Current index. */