293 #define NSP32_DEBUG_INTR		BIT(3)  macro
428 	nsp32_dbg(NSP32_DEBUG_INTR, "timer=%d", time);
431 		nsp32_dbg(NSP32_DEBUG_INTR, "timer set overflow");
1166 	nsp32_dbg(NSP32_DEBUG_INTR,   in do_nsp32_isr()
1170 		nsp32_dbg(NSP32_DEBUG_INTR, "shared interrupt: irq other 0x%x", irq_stat);  in do_nsp32_isr()
1192 		nsp32_dbg(NSP32_DEBUG_INTR, "timer stop");  in do_nsp32_isr()
1227 			nsp32_dbg(NSP32_DEBUG_INTR,  in do_nsp32_isr()
1252 			nsp32_dbg(NSP32_DEBUG_INTR, "MsgOut phase processed");  in do_nsp32_isr()
1264 			nsp32_dbg(NSP32_DEBUG_INTR,  in do_nsp32_isr()
1268 			nsp32_dbg(NSP32_DEBUG_INTR, "BMCNT=0x%lx",   in do_nsp32_isr()
1270 			nsp32_dbg(NSP32_DEBUG_INTR, "addr=0x%lx",   in do_nsp32_isr()
1272 			nsp32_dbg(NSP32_DEBUG_INTR, "SACK=0x%lx",   in do_nsp32_isr()
1274 			nsp32_dbg(NSP32_DEBUG_INTR, "SSACK=0x%lx",   in do_nsp32_isr()
1333 			nsp32_dbg(NSP32_DEBUG_INTR, "Command phase processed");  in do_nsp32_isr()
1345 		nsp32_dbg(NSP32_DEBUG_INTR, "FIFO IRQ");  in do_nsp32_isr()
1349 			nsp32_dbg(NSP32_DEBUG_INTR, "fifo/write");  in do_nsp32_isr()
1356 			nsp32_dbg(NSP32_DEBUG_INTR, "fifo/read");  in do_nsp32_isr()
1363 			nsp32_dbg(NSP32_DEBUG_INTR, "fifo/status");  in do_nsp32_isr()
1369 			nsp32_dbg(NSP32_DEBUG_INTR, "fifo/other phase");  in do_nsp32_isr()
1370 			nsp32_dbg(NSP32_DEBUG_INTR, "irq_stat=0x%x trans_stat=0x%x", irq_stat, trans_stat);  in do_nsp32_isr()
1380 		nsp32_dbg(NSP32_DEBUG_INTR, "phase change IRQ");  in do_nsp32_isr()
1384 			nsp32_dbg(NSP32_DEBUG_INTR, "phase chg/msg in");  in do_nsp32_isr()
1399 		nsp32_dbg(NSP32_DEBUG_INTR, "PCI IRQ occurred");  in do_nsp32_isr()
1414 	nsp32_dbg(NSP32_DEBUG_INTR,  in do_nsp32_isr()
1426 	nsp32_dbg(NSP32_DEBUG_INTR, "exit");  in do_nsp32_isr()