Lines Matching refs:tmp
38 u32 tmp, setting_0 = 0, setting_1 = 0; in set_phy_tuning() local
81 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_tuning()
82 tmp &= ~(0xFBE << 16); in set_phy_tuning()
83 tmp |= (((phy_tuning.trans_emp_en << 11) | in set_phy_tuning()
86 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_tuning()
90 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_tuning()
91 tmp &= ~(0xC000); in set_phy_tuning()
92 tmp |= (phy_tuning.trans_amp_adj << 14); in set_phy_tuning()
93 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_tuning()
100 u32 tmp; in set_phy_ffe_tuning() local
115 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_ffe_tuning()
116 tmp &= ~0xFF; in set_phy_ffe_tuning()
119 tmp |= ((0x1 << 7) | in set_phy_ffe_tuning()
123 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_ffe_tuning()
130 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_ffe_tuning()
131 tmp &= ~0x40001; in set_phy_ffe_tuning()
134 tmp |= (0 << 18); in set_phy_ffe_tuning()
135 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_ffe_tuning()
143 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_ffe_tuning()
144 tmp &= ~0xFFF; in set_phy_ffe_tuning()
147 tmp |= ((0x3F << 6) | (0x0 << 0)); in set_phy_ffe_tuning()
148 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_ffe_tuning()
155 tmp = mvs_read_port_vsr_data(mvi, phy_id); in set_phy_ffe_tuning()
156 tmp &= ~0x8; in set_phy_ffe_tuning()
159 tmp |= (0 << 3); in set_phy_ffe_tuning()
160 mvs_write_port_vsr_data(mvi, phy_id, tmp); in set_phy_ffe_tuning()
247 u32 tmp; in mvs_94xx_enable_xmt() local
249 tmp = mr32(MVS_PCS); in mvs_94xx_enable_xmt()
250 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2); in mvs_94xx_enable_xmt()
251 mw32(MVS_PCS, tmp); in mvs_94xx_enable_xmt()
256 u32 tmp; in mvs_94xx_phy_reset() local
260 tmp = mvs_read_port_cfg_data(mvi, phy_id); in mvs_94xx_phy_reset()
261 mvs_write_port_cfg_data(mvi, phy_id, tmp|0x20000000); in mvs_94xx_phy_reset()
262 mvs_write_port_cfg_data(mvi, phy_id, tmp|0x100000); in mvs_94xx_phy_reset()
265 tmp = mvs_read_port_irq_stat(mvi, phy_id); in mvs_94xx_phy_reset()
266 tmp &= ~PHYEV_RDY_CH; in mvs_94xx_phy_reset()
267 mvs_write_port_irq_stat(mvi, phy_id, tmp); in mvs_94xx_phy_reset()
269 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_94xx_phy_reset()
270 tmp |= PHY_RST_HARD; in mvs_94xx_phy_reset()
271 mvs_write_phy_ctl(mvi, phy_id, tmp); in mvs_94xx_phy_reset()
273 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_94xx_phy_reset()
276 } while ((tmp & PHY_RST_HARD) && delay); in mvs_94xx_phy_reset()
280 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_94xx_phy_reset()
281 tmp |= PHY_RST; in mvs_94xx_phy_reset()
282 mvs_write_phy_ctl(mvi, phy_id, tmp); in mvs_94xx_phy_reset()
288 u32 tmp; in mvs_94xx_phy_disable() local
290 tmp = mvs_read_port_vsr_data(mvi, phy_id); in mvs_94xx_phy_disable()
291 mvs_write_port_vsr_data(mvi, phy_id, tmp | 0x00800000); in mvs_94xx_phy_disable()
296 u32 tmp; in mvs_94xx_phy_enable() local
312 tmp = mvs_read_port_vsr_data(mvi, phy_id); in mvs_94xx_phy_enable()
313 tmp |= bit(0); in mvs_94xx_phy_enable()
314 mvs_write_port_vsr_data(mvi, phy_id, tmp & 0xfd7fffff); in mvs_94xx_phy_enable()
320 u32 tmp; in mvs_94xx_sgpio_init() local
322 tmp = mr32(MVS_HST_CHIP_CONFIG); in mvs_94xx_sgpio_init()
323 tmp |= 0x100; in mvs_94xx_sgpio_init()
324 mw32(MVS_HST_CHIP_CONFIG, tmp); in mvs_94xx_sgpio_init()
366 u32 tmp, cctl; in mvs_94xx_init() local
372 tmp = mr32(MVS_PHY_CTL); in mvs_94xx_init()
373 tmp &= ~PCTL_PWR_OFF; in mvs_94xx_init()
374 tmp |= PCTL_PHY_DSBL; in mvs_94xx_init()
375 mw32(MVS_PHY_CTL, tmp); in mvs_94xx_init()
387 tmp = mr32(MVS_PHY_CTL); in mvs_94xx_init()
388 tmp &= ~PCTL_PWR_OFF; in mvs_94xx_init()
389 tmp |= PCTL_COM_ON; in mvs_94xx_init()
390 tmp &= ~PCTL_PHY_DSBL; in mvs_94xx_init()
391 tmp |= PCTL_LINK_RST; in mvs_94xx_init()
392 mw32(MVS_PHY_CTL, tmp); in mvs_94xx_init()
394 tmp &= ~PCTL_LINK_RST; in mvs_94xx_init()
395 mw32(MVS_PHY_CTL, tmp); in mvs_94xx_init()
430 tmp = mvs_cr32(mvi, CMD_SAS_CTL1); in mvs_94xx_init()
434 tmp &= ~0xffff; in mvs_94xx_init()
435 tmp |= 0x007f; in mvs_94xx_init()
436 mvs_cw32(mvi, CMD_SAS_CTL1, tmp); in mvs_94xx_init()
441 tmp = mr32(MVS_PA_VSR_PORT); in mvs_94xx_init()
442 tmp &= 0xFFFF00FF; in mvs_94xx_init()
443 tmp |= 0x00003300; in mvs_94xx_init()
444 mw32(MVS_PA_VSR_PORT, tmp); in mvs_94xx_init()
488 tmp = mvs_read_port_irq_stat(mvi, i); in mvs_94xx_init()
489 tmp &= ~PHYEV_SIG_FIS; in mvs_94xx_init()
490 mvs_write_port_irq_stat(mvi, i, tmp); in mvs_94xx_init()
493 tmp = PHYEV_RDY_CH | PHYEV_BROAD_CH | in mvs_94xx_init()
495 mvs_write_port_irq_mask(mvi, i, tmp); in mvs_94xx_init()
509 tmp = mr32(MVS_PCS); in mvs_94xx_init()
510 tmp |= PCS_CMD_RST; in mvs_94xx_init()
511 tmp &= ~PCS_SELF_CLEAR; in mvs_94xx_init()
512 mw32(MVS_PCS, tmp); in mvs_94xx_init()
517 tmp = 0; in mvs_94xx_init()
524 tmp = 0x10000 | interrupt_coalescing; in mvs_94xx_init()
525 mw32(MVS_INT_COAL_TMOUT, tmp); in mvs_94xx_init()
536 tmp = (CINT_PORT_MASK | CINT_DONE | CINT_MEM | CINT_SRS | CINT_CI_STOP | in mvs_94xx_init()
538 tmp |= CINT_PHY_MASK; in mvs_94xx_init()
539 mw32(MVS_INT_MASK, tmp); in mvs_94xx_init()
541 tmp = mvs_cr32(mvi, CMD_LINK_TIMER); in mvs_94xx_init()
542 tmp |= 0xFFFF0000; in mvs_94xx_init()
543 mvs_cw32(mvi, CMD_LINK_TIMER, tmp); in mvs_94xx_init()
546 tmp = 0x003F003F; in mvs_94xx_init()
547 mvs_cw32(mvi, CMD_PL_TIMER, tmp); in mvs_94xx_init()
550 tmp = mvs_cr32(mvi, CMD_PORT_LAYER_TIMER1); in mvs_94xx_init()
551 tmp |= 0xFFFF007F; in mvs_94xx_init()
552 mvs_cw32(mvi, CMD_PORT_LAYER_TIMER1, tmp); in mvs_94xx_init()
556 tmp = mvs_cr32(mvi, CMD_SL_MODE0); in mvs_94xx_init()
557 tmp |= 0x00000300; in mvs_94xx_init()
559 tmp &= 0xFFFFFFFE; in mvs_94xx_init()
560 mvs_cw32(mvi, CMD_SL_MODE0, tmp); in mvs_94xx_init()
595 u32 tmp; in mvs_94xx_interrupt_enable() local
597 tmp = mr32(MVS_GBL_CTL); in mvs_94xx_interrupt_enable()
598 tmp |= (MVS_IRQ_SAS_A | MVS_IRQ_SAS_B); in mvs_94xx_interrupt_enable()
599 mw32(MVS_GBL_INT_STAT, tmp); in mvs_94xx_interrupt_enable()
600 writel(tmp, regs + 0x0C); in mvs_94xx_interrupt_enable()
601 writel(tmp, regs + 0x10); in mvs_94xx_interrupt_enable()
602 writel(tmp, regs + 0x14); in mvs_94xx_interrupt_enable()
603 writel(tmp, regs + 0x18); in mvs_94xx_interrupt_enable()
604 mw32(MVS_GBL_CTL, tmp); in mvs_94xx_interrupt_enable()
610 u32 tmp; in mvs_94xx_interrupt_disable() local
612 tmp = mr32(MVS_GBL_CTL); in mvs_94xx_interrupt_disable()
614 tmp &= ~(MVS_IRQ_SAS_A | MVS_IRQ_SAS_B); in mvs_94xx_interrupt_disable()
615 mw32(MVS_GBL_INT_STAT, tmp); in mvs_94xx_interrupt_disable()
616 writel(tmp, regs + 0x0C); in mvs_94xx_interrupt_disable()
617 writel(tmp, regs + 0x10); in mvs_94xx_interrupt_disable()
618 writel(tmp, regs + 0x14); in mvs_94xx_interrupt_disable()
619 writel(tmp, regs + 0x18); in mvs_94xx_interrupt_disable()
620 mw32(MVS_GBL_CTL, tmp); in mvs_94xx_interrupt_disable()
653 u32 tmp; in mvs_94xx_command_active() local
654 tmp = mvs_cr32(mvi, MVS_COMMAND_ACTIVE+(slot_idx >> 3)); in mvs_94xx_command_active()
655 if (tmp & 1 << (slot_idx % 32)) { in mvs_94xx_command_active()
656 mv_printk("command active %08X, slot [%x].\n", tmp, slot_idx); in mvs_94xx_command_active()
660 tmp = mvs_cr32(mvi, in mvs_94xx_command_active()
662 } while (tmp & 1 << (slot_idx % 32)); in mvs_94xx_command_active()
670 u32 tmp; in mvs_94xx_clear_srs_irq() local
673 tmp = mr32(MVS_INT_STAT_SRS_0); in mvs_94xx_clear_srs_irq()
674 if (tmp) { in mvs_94xx_clear_srs_irq()
675 mv_dprintk("check SRS 0 %08X.\n", tmp); in mvs_94xx_clear_srs_irq()
676 mw32(MVS_INT_STAT_SRS_0, tmp); in mvs_94xx_clear_srs_irq()
678 tmp = mr32(MVS_INT_STAT_SRS_1); in mvs_94xx_clear_srs_irq()
679 if (tmp) { in mvs_94xx_clear_srs_irq()
680 mv_dprintk("check SRS 1 %08X.\n", tmp); in mvs_94xx_clear_srs_irq()
681 mw32(MVS_INT_STAT_SRS_1, tmp); in mvs_94xx_clear_srs_irq()
685 tmp = mr32(MVS_INT_STAT_SRS_1); in mvs_94xx_clear_srs_irq()
687 tmp = mr32(MVS_INT_STAT_SRS_0); in mvs_94xx_clear_srs_irq()
689 if (tmp & (1 << (reg_set % 32))) { in mvs_94xx_clear_srs_irq()
703 u32 tmp; in mvs_94xx_issue_stop() local
706 tmp = mr32(MVS_INT_STAT); in mvs_94xx_issue_stop()
707 mw32(MVS_INT_STAT, tmp | CINT_CI_STOP); in mvs_94xx_issue_stop()
708 tmp = mr32(MVS_PCS) | 0xFF00; in mvs_94xx_issue_stop()
709 mw32(MVS_PCS, tmp); in mvs_94xx_issue_stop()
898 u32 tmp; in mvs_94xx_phy_set_link_rate() local
900 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_94xx_phy_set_link_rate()
904 tmp &= ~(0x3 << 12); in mvs_94xx_phy_set_link_rate()
905 tmp |= lrmax; in mvs_94xx_phy_set_link_rate()
907 mvs_write_phy_ctl(mvi, phy_id, tmp); in mvs_94xx_phy_set_link_rate()
913 u32 tmp; in mvs_94xx_clear_active_cmds() local
915 tmp = mr32(MVS_STP_REG_SET_0); in mvs_94xx_clear_active_cmds()
917 mw32(MVS_STP_REG_SET_0, tmp); in mvs_94xx_clear_active_cmds()
918 tmp = mr32(MVS_STP_REG_SET_1); in mvs_94xx_clear_active_cmds()
920 mw32(MVS_STP_REG_SET_1, tmp); in mvs_94xx_clear_active_cmds()
1021 u32 tmp = 0; in mvs_94xx_tune_interrupt() local
1035 tmp = 0x10000 | time; in mvs_94xx_tune_interrupt()
1036 mw32(MVS_INT_COAL_TMOUT, tmp); in mvs_94xx_tune_interrupt()