203 		if ((NCR5380_read(reg1) & bit1) == val1)  in NCR5380_poll_politely2()
205 		if ((NCR5380_read(reg2) & bit2) == val2)  in NCR5380_poll_politely2()
216 		if ((NCR5380_read(reg1) & bit1) == val1)  in NCR5380_poll_politely2()
218 		if ((NCR5380_read(reg2) & bit2) == val2)  in NCR5380_poll_politely2()
286 	status = NCR5380_read(STATUS_REG);  in NCR5380_print()
287 	mr = NCR5380_read(MODE_REG);  in NCR5380_print()
288 	icr = NCR5380_read(INITIATOR_COMMAND_REG);  in NCR5380_print()
289 	basr = NCR5380_read(BUS_AND_STATUS_REG);  in NCR5380_print()
336 	status = NCR5380_read(STATUS_REG);  in NCR5380_print_phase()
433 		NCR5380_read(STATUS_REG);  in NCR5380_init()
462 	for (pass = 1; (NCR5380_read(STATUS_REG) & SR_BSY) && pass <= 6; ++pass) {  in NCR5380_maybe_reset_bus()
750 			if ((NCR5380_read(BUS_AND_STATUS_REG) &  in NCR5380_dma_complete()
753 				saved_data = NCR5380_read(INPUT_DATA_REG);  in NCR5380_dma_complete()
767 	if ((NCR5380_read(BUS_AND_STATUS_REG) & (BASR_PHASE_MATCH | BASR_ACK)) ==  in NCR5380_dma_complete()
770 		       NCR5380_read(BUS_AND_STATUS_REG));  in NCR5380_dma_complete()
779 	NCR5380_read(RESET_PARITY_INTERRUPT_REG);  in NCR5380_dma_complete()
792 		if ((NCR5380_read(STATUS_REG) & PHASE_MASK) == p && (p & SR_IO)) {  in NCR5380_dma_complete()
856 	basr = NCR5380_read(BUS_AND_STATUS_REG);  in NCR5380_intr()
858 		unsigned char mr = NCR5380_read(MODE_REG);  in NCR5380_intr()
859 		unsigned char sr = NCR5380_read(STATUS_REG);  in NCR5380_intr()
877 				NCR5380_read(RESET_PARITY_INTERRUPT_REG);  in NCR5380_intr()
879 		} else if ((NCR5380_read(CURRENT_SCSI_DATA_REG) & hostdata->id_mask) &&  in NCR5380_intr()
883 			NCR5380_read(RESET_PARITY_INTERRUPT_REG);  in NCR5380_intr()
895 			NCR5380_read(RESET_PARITY_INTERRUPT_REG);  in NCR5380_intr()
995 	if (!(NCR5380_read(MODE_REG) & MR_ARBITRATE)) {  in NCR5380_select()
1016 	if ((NCR5380_read(INITIATOR_COMMAND_REG) & ICR_ARBITRATION_LOST) ||  in NCR5380_select()
1017 	    (NCR5380_read(CURRENT_SCSI_DATA_REG) & hostdata->id_higher_mask) ||  in NCR5380_select()
1018 	    (NCR5380_read(INITIATOR_COMMAND_REG) & ICR_ARBITRATION_LOST)) {  in NCR5380_select()
1045 	if (!(NCR5380_read(MODE_REG) & MR_ARBITRATE))  in NCR5380_select()
1120 	if ((NCR5380_read(STATUS_REG) & (SR_SEL | SR_IO)) == (SR_SEL | SR_IO)) {  in NCR5380_select()
1266 		if ((NCR5380_read(STATUS_REG) & PHASE_MASK) != p) {  in NCR5380_transfer_pio()
1276 			*d = NCR5380_read(CURRENT_SCSI_DATA_REG);  in NCR5380_transfer_pio()
1334 	tmp = NCR5380_read(STATUS_REG);  in NCR5380_transfer_pio()
1369 	              PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG) & PHASE_MASK));  in do_reset()
1373 	(void)NCR5380_read(RESET_PARITY_INTERRUPT_REG);  in do_reset()
1409 	tmp = NCR5380_read(STATUS_REG) & PHASE_MASK;  in do_abort()
1470 	if ((tmp = (NCR5380_read(STATUS_REG) & PHASE_MASK)) != p) {  in NCR5380_transfer_dma()
1614 			d[*count - 1] = NCR5380_read(INPUT_DATA_REG);  in NCR5380_transfer_dma()
1669 		tmp = NCR5380_read(STATUS_REG);  in NCR5380_information_transfer()
1706 				while (NCR5380_read(STATUS_REG) & SR_REQ)  in NCR5380_information_transfer()
2016 	target_mask = NCR5380_read(CURRENT_SCSI_DATA_REG) & ~(hostdata->id_mask);  in NCR5380_reselect()
2047 		if ((NCR5380_read(STATUS_REG) & (SR_BSY | SR_SEL)) == 0)  in NCR5380_reselect()
2060 	msg[0] = NCR5380_read(CURRENT_SCSI_DATA_REG);  in NCR5380_reselect()