76 	void __iomem *reg_base;  member
103 	val = readl(wcss->reg_base + Q6SS_RESET_REG);  in q6v5_wcss_reset()
105 	writel(val, wcss->reg_base + Q6SS_RESET_REG);  in q6v5_wcss_reset()
108 	val = readl(wcss->reg_base + Q6SS_XO_CBCR);  in q6v5_wcss_reset()
110 	writel(val, wcss->reg_base + Q6SS_XO_CBCR);  in q6v5_wcss_reset()
113 	ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR,  in q6v5_wcss_reset()
122 	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_wcss_reset()
124 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_wcss_reset()
129 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_wcss_reset()
132 	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_wcss_reset()
134 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_wcss_reset()
138 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_wcss_reset()
141 	val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);  in q6v5_wcss_reset()
144 		writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL);  in q6v5_wcss_reset()
150 		val |= readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);  in q6v5_wcss_reset()
154 	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_wcss_reset()
156 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_wcss_reset()
160 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_wcss_reset()
163 	val = readl(wcss->reg_base + Q6SS_RESET_REG);  in q6v5_wcss_reset()
165 	writel(val, wcss->reg_base + Q6SS_RESET_REG);  in q6v5_wcss_reset()
168 	val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);  in q6v5_wcss_reset()
170 	writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);  in q6v5_wcss_reset()
173 	val = readl(wcss->reg_base + Q6SS_RESET_REG);  in q6v5_wcss_reset()
175 	writel(val, wcss->reg_base + Q6SS_RESET_REG);  in q6v5_wcss_reset()
215 	writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB);  in q6v5_wcss_start()
326 	val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);  in q6v5_q6_powerdown()
328 	writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);  in q6v5_q6_powerdown()
331 	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_q6_powerdown()
333 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_q6_powerdown()
337 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_q6_powerdown()
341 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_q6_powerdown()
345 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_q6_powerdown()
349 		val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);  in q6v5_q6_powerdown()
351 		writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL);  in q6v5_q6_powerdown()
356 	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_q6_powerdown()
358 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_q6_powerdown()
362 	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);  in q6v5_q6_powerdown()
366 	ret = readl_poll_timeout(wcss->reg_base + Q6SS_BHS_STATUS,  in q6v5_q6_powerdown()
471 	wcss->reg_base = devm_ioremap_resource(&pdev->dev, res);  in q6v5_wcss_init_mmio()
472 	if (IS_ERR(wcss->reg_base))  in q6v5_wcss_init_mmio()
473 		return PTR_ERR(wcss->reg_base);  in q6v5_wcss_init_mmio()