62 #define QDSP6SS_PWR_CTL_REG		0x030  macro
526 		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
528 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
529 		val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
534 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
537 		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
539 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
543 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
560 		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
562 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
570 		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
572 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
573 		val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
579 		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
582 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
584 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
586 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
588 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
592 	writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
872 		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5_mba_reclaim()
875 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5_mba_reclaim()