38 	struct sh_pfc *pfc;  member
52 	return pmx->pfc->info->nr_groups;  in sh_pfc_get_groups_count()
60 	return pmx->pfc->info->groups[selector].name;  in sh_pfc_get_group_name()
68 	*pins = pmx->pfc->info->groups[selector].pins;  in sh_pfc_get_group_pins()
69 	*num_pins = pmx->pfc->info->groups[selector].nr_pins;  in sh_pfc_get_group_pins()
108 	struct device *dev = pmx->pfc->dev;  in sh_pfc_dt_subnode_to_map()
263 	struct device *dev = pmx->pfc->dev;  in sh_pfc_dt_node_to_map()
318 	return pmx->pfc->info->nr_functions;  in sh_pfc_get_functions_count()
326 	return pmx->pfc->info->functions[selector].name;  in sh_pfc_get_function_name()
336 	*groups = pmx->pfc->info->functions[selector].groups;  in sh_pfc_get_function_groups()
337 	*num_groups = pmx->pfc->info->functions[selector].nr_groups;  in sh_pfc_get_function_groups()
346 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_func_set_mux()  local
347 	const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];  in sh_pfc_func_set_mux()
354 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_func_set_mux()
357 		int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);  in sh_pfc_func_set_mux()
369 		ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);  in sh_pfc_func_set_mux()
376 		int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);  in sh_pfc_func_set_mux()
384 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_func_set_mux()
393 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_gpio_request_enable()  local
394 	int idx = sh_pfc_get_pin_index(pfc, offset);  in sh_pfc_gpio_request_enable()
399 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_gpio_request_enable()
401 	if (!pfc->gpio) {  in sh_pfc_gpio_request_enable()
405 		const struct sh_pfc_pin *pin = &pfc->info->pins[idx];  in sh_pfc_gpio_request_enable()
407 		ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);  in sh_pfc_gpio_request_enable()
417 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_gpio_request_enable()
427 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_gpio_disable_free()  local
428 	int idx = sh_pfc_get_pin_index(pfc, offset);  in sh_pfc_gpio_disable_free()
432 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_gpio_disable_free()
436 		sh_pfc_config_mux(pfc, cfg->mux_mark, PINMUX_TYPE_FUNCTION);  in sh_pfc_gpio_disable_free()
437 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_gpio_disable_free()
445 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_gpio_set_direction()  local
447 	int idx = sh_pfc_get_pin_index(pfc, offset);  in sh_pfc_gpio_set_direction()
448 	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];  in sh_pfc_gpio_set_direction()
462 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_gpio_set_direction()
464 	ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);  in sh_pfc_gpio_set_direction()
469 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_gpio_set_direction()
483 static u32 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc,  in sh_pfc_pinconf_find_drive_strength_reg()  argument
490 	for (reg = pfc->info->drive_regs; reg->reg; ++reg) {  in sh_pfc_pinconf_find_drive_strength_reg()
506 static int sh_pfc_pinconf_get_drive_strength(struct sh_pfc *pfc,  in sh_pfc_pinconf_get_drive_strength()  argument
515 	reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);  in sh_pfc_pinconf_get_drive_strength()
519 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_get_drive_strength()
520 	val = sh_pfc_read(pfc, reg);  in sh_pfc_pinconf_get_drive_strength()
521 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_get_drive_strength()
531 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,  in sh_pfc_pinconf_set_drive_strength()  argument
541 	reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);  in sh_pfc_pinconf_set_drive_strength()
555 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_set_drive_strength()
557 	val = sh_pfc_read(pfc, reg);  in sh_pfc_pinconf_set_drive_strength()
561 	sh_pfc_write(pfc, reg, val);  in sh_pfc_pinconf_set_drive_strength()
563 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_set_drive_strength()
569 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,  in sh_pfc_pinconf_validate()  argument
572 	int idx = sh_pfc_get_pin_index(pfc, _pin);  in sh_pfc_pinconf_validate()
573 	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];  in sh_pfc_pinconf_validate()
600 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_pinconf_get()  local
605 	if (!sh_pfc_pinconf_validate(pfc, _pin, param))  in sh_pfc_pinconf_get()
614 		if (!pfc->info->ops || !pfc->info->ops->get_bias)  in sh_pfc_pinconf_get()
617 		spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_get()
618 		bias = pfc->info->ops->get_bias(pfc, _pin);  in sh_pfc_pinconf_get()
619 		spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_get()
631 		ret = sh_pfc_pinconf_get_drive_strength(pfc, _pin);  in sh_pfc_pinconf_get()
643 		if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)  in sh_pfc_pinconf_get()
646 		bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl);  in sh_pfc_pinconf_get()
650 		spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_get()
651 		val = sh_pfc_read(pfc, pocctrl);  in sh_pfc_pinconf_get()
652 		spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_get()
670 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_pinconf_set()  local
678 		if (!sh_pfc_pinconf_validate(pfc, _pin, param))  in sh_pfc_pinconf_set()
685 			if (!pfc->info->ops || !pfc->info->ops->set_bias)  in sh_pfc_pinconf_set()
688 			spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_set()
689 			pfc->info->ops->set_bias(pfc, _pin, param);  in sh_pfc_pinconf_set()
690 			spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_set()
699 			ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);  in sh_pfc_pinconf_set()
711 			if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)  in sh_pfc_pinconf_set()
714 			bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl);  in sh_pfc_pinconf_set()
721 			spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_set()
722 			val = sh_pfc_read(pfc, pocctrl);  in sh_pfc_pinconf_set()
727 			sh_pfc_write(pfc, pocctrl, val);  in sh_pfc_pinconf_set()
728 			spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_set()
750 	pins = pmx->pfc->info->groups[group].pins;  in sh_pfc_pinconf_group_set()
751 	num_pins = pmx->pfc->info->groups[group].nr_pins;  in sh_pfc_pinconf_group_set()
771 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)  in sh_pfc_map_pins()  argument
776 	pmx->pins = devm_kcalloc(pfc->dev,  in sh_pfc_map_pins()
777 				 pfc->info->nr_pins, sizeof(*pmx->pins),  in sh_pfc_map_pins()
782 	pmx->configs = devm_kcalloc(pfc->dev,  in sh_pfc_map_pins()
783 				    pfc->info->nr_pins, sizeof(*pmx->configs),  in sh_pfc_map_pins()
788 	for (i = 0; i < pfc->info->nr_pins; ++i) {  in sh_pfc_map_pins()
789 		const struct sh_pfc_pin *info = &pfc->info->pins[i];  in sh_pfc_map_pins()
800 int sh_pfc_register_pinctrl(struct sh_pfc *pfc)  in sh_pfc_register_pinctrl()  argument
805 	pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);  in sh_pfc_register_pinctrl()
809 	pmx->pfc = pfc;  in sh_pfc_register_pinctrl()
811 	ret = sh_pfc_map_pins(pfc, pmx);  in sh_pfc_register_pinctrl()
821 	pmx->pctl_desc.npins = pfc->info->nr_pins;  in sh_pfc_register_pinctrl()
823 	ret = devm_pinctrl_register_and_init(pfc->dev, &pmx->pctl_desc, pmx,  in sh_pfc_register_pinctrl()
826 		dev_err(pfc->dev, "could not register: %i\n", ret);  in sh_pfc_register_pinctrl()