Lines Matching refs:pctrl

52 	struct pinctrl_dev *pctrl;  member
70 static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \
73 return readl(pctrl->regs[g->tile] + g->name##_reg); \
75 static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
78 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
89 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in MSM_ACCESSOR() local
91 return pctrl->soc->ngroups; in MSM_ACCESSOR()
97 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_group_name() local
99 return pctrl->soc->groups[group].name; in msm_get_group_name()
107 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_group_pins() local
109 *pins = pctrl->soc->groups[group].pins; in msm_get_group_pins()
110 *num_pins = pctrl->soc->groups[group].npins; in msm_get_group_pins()
124 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_pinmux_request() local
125 struct gpio_chip *chip = &pctrl->chip; in msm_pinmux_request()
132 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_functions_count() local
134 return pctrl->soc->nfunctions; in msm_get_functions_count()
140 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_function_name() local
142 return pctrl->soc->functions[function].name; in msm_get_function_name()
150 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_function_groups() local
152 *groups = pctrl->soc->functions[function].groups; in msm_get_function_groups()
153 *num_groups = pctrl->soc->functions[function].ngroups; in msm_get_function_groups()
161 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_pinmux_set_mux() local
167 g = &pctrl->soc->groups[group]; in msm_pinmux_set_mux()
178 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_pinmux_set_mux()
180 val = msm_readl_ctl(pctrl, g); in msm_pinmux_set_mux()
183 msm_writel_ctl(val, pctrl, g); in msm_pinmux_set_mux()
185 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_pinmux_set_mux()
194 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_pinmux_request_gpio() local
195 const struct msm_pingroup *g = &pctrl->soc->groups[offset]; in msm_pinmux_request_gpio()
214 static int msm_config_reg(struct msm_pinctrl *pctrl, in msm_config_reg() argument
260 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_config_group_get() local
268 g = &pctrl->soc->groups[group]; in msm_config_group_get()
270 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_get()
274 val = msm_readl_ctl(pctrl, g); in msm_config_group_get()
290 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
298 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
313 val = msm_readl_io(pctrl, g); in msm_config_group_get()
337 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_config_group_set() local
347 g = &pctrl->soc->groups[group]; in msm_config_group_set()
353 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_set()
366 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
372 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
386 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
387 val = msm_readl_io(pctrl, g); in msm_config_group_set()
392 msm_writel_io(val, pctrl, g); in msm_config_group_set()
393 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
403 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", in msm_config_group_set()
410 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); in msm_config_group_set()
414 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
415 val = msm_readl_ctl(pctrl, g); in msm_config_group_set()
418 msm_writel_ctl(val, pctrl, g); in msm_config_group_set()
419 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
434 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_direction_input() local
438 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_input()
440 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_input()
442 val = msm_readl_ctl(pctrl, g); in msm_gpio_direction_input()
444 msm_writel_ctl(val, pctrl, g); in msm_gpio_direction_input()
446 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_input()
454 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_direction_output() local
458 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_output()
460 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_output()
462 val = msm_readl_io(pctrl, g); in msm_gpio_direction_output()
467 msm_writel_io(val, pctrl, g); in msm_gpio_direction_output()
469 val = msm_readl_ctl(pctrl, g); in msm_gpio_direction_output()
471 msm_writel_ctl(val, pctrl, g); in msm_gpio_direction_output()
473 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_output()
480 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_get_direction() local
484 g = &pctrl->soc->groups[offset]; in msm_gpio_get_direction()
486 val = msm_readl_ctl(pctrl, g); in msm_gpio_get_direction()
495 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_get() local
498 g = &pctrl->soc->groups[offset]; in msm_gpio_get()
500 val = msm_readl_io(pctrl, g); in msm_gpio_get()
507 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_set() local
511 g = &pctrl->soc->groups[offset]; in msm_gpio_set()
513 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_set()
515 val = msm_readl_io(pctrl, g); in msm_gpio_set()
520 msm_writel_io(val, pctrl, g); in msm_gpio_set()
522 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_set()
535 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_dbg_show_one() local
559 g = &pctrl->soc->groups[offset]; in msm_gpio_dbg_show_one()
560 ctl_reg = msm_readl_ctl(pctrl, g); in msm_gpio_dbg_show_one()
561 io_reg = msm_readl_io(pctrl, g); in msm_gpio_dbg_show_one()
576 if (pctrl->soc->pull_no_keeper) in msm_gpio_dbg_show_one()
600 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_init_valid_mask() local
603 const int *reserved = pctrl->soc->reserved_gpios; in msm_gpio_init_valid_mask()
611 dev_err(pctrl->dev, "invalid list of reserved GPIOs\n"); in msm_gpio_init_valid_mask()
621 len = ret = device_property_count_u16(pctrl->dev, "gpios"); in msm_gpio_init_valid_mask()
632 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len); in msm_gpio_init_valid_mask()
634 dev_err(pctrl->dev, "could not read list of GPIOs\n"); in msm_gpio_init_valid_mask()
678 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, in msm_gpio_update_dual_edge_pos() argument
687 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
689 pol = msm_readl_intr_cfg(pctrl, g); in msm_gpio_update_dual_edge_pos()
691 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_update_dual_edge_pos()
693 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
694 intstat = msm_readl_intr_status(pctrl, g); in msm_gpio_update_dual_edge_pos()
698 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", in msm_gpio_update_dual_edge_pos()
705 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_mask() local
710 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_mask()
712 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_mask()
714 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_mask()
739 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_mask()
741 clear_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_mask()
743 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_mask()
749 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_clear_unmask() local
754 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_clear_unmask()
756 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_clear_unmask()
764 val = msm_readl_intr_status(pctrl, g); in msm_gpio_irq_clear_unmask()
766 msm_writel_intr_status(val, pctrl, g); in msm_gpio_irq_clear_unmask()
769 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_clear_unmask()
772 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_clear_unmask()
774 set_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_clear_unmask()
776 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_clear_unmask()
793 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_ack() local
798 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_ack()
800 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_ack()
802 val = msm_readl_intr_status(pctrl, g); in msm_gpio_irq_ack()
807 msm_writel_intr_status(val, pctrl, g); in msm_gpio_irq_ack()
809 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
810 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_ack()
812 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_ack()
818 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_set_type() local
823 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_set_type()
825 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_set_type()
831 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
833 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
836 val = msm_readl_intr_target(pctrl, g); in msm_gpio_irq_set_type()
839 msm_writel_intr_target(val, pctrl, g); in msm_gpio_irq_set_type()
846 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_set_type()
894 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_set_type()
896 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_set_type()
897 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_set_type()
899 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_set_type()
912 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_set_wake() local
915 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_set_wake()
917 irq_set_irq_wake(pctrl->irq, on); in msm_gpio_irq_set_wake()
919 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_set_wake()
927 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_reqres() local
933 ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq); in msm_gpio_irq_reqres()
963 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_handler() local
976 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { in msm_gpio_irq_handler()
977 g = &pctrl->soc->groups[i]; in msm_gpio_irq_handler()
978 val = msm_readl_intr_status(pctrl, g); in msm_gpio_irq_handler()
993 static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl) in msm_gpio_needs_valid_mask() argument
995 if (pctrl->soc->reserved_gpios) in msm_gpio_needs_valid_mask()
998 return device_property_count_u16(pctrl->dev, "gpios") > 0; in msm_gpio_needs_valid_mask()
1001 static int msm_gpio_init(struct msm_pinctrl *pctrl) in msm_gpio_init() argument
1006 unsigned ngpio = pctrl->soc->ngpios; in msm_gpio_init()
1011 chip = &pctrl->chip; in msm_gpio_init()
1014 chip->label = dev_name(pctrl->dev); in msm_gpio_init()
1015 chip->parent = pctrl->dev; in msm_gpio_init()
1017 chip->of_node = pctrl->dev->of_node; in msm_gpio_init()
1018 if (msm_gpio_needs_valid_mask(pctrl)) in msm_gpio_init()
1021 pctrl->irq_chip.name = "msmgpio"; in msm_gpio_init()
1022 pctrl->irq_chip.irq_enable = msm_gpio_irq_enable; in msm_gpio_init()
1023 pctrl->irq_chip.irq_mask = msm_gpio_irq_mask; in msm_gpio_init()
1024 pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask; in msm_gpio_init()
1025 pctrl->irq_chip.irq_ack = msm_gpio_irq_ack; in msm_gpio_init()
1026 pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type; in msm_gpio_init()
1027 pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake; in msm_gpio_init()
1028 pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres; in msm_gpio_init()
1029 pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres; in msm_gpio_init()
1032 girq->chip = &pctrl->irq_chip; in msm_gpio_init()
1035 girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents), in msm_gpio_init()
1041 girq->parents[0] = pctrl->irq; in msm_gpio_init()
1043 ret = gpiochip_add_data(&pctrl->chip, pctrl); in msm_gpio_init()
1045 dev_err(pctrl->dev, "Failed register gpiochip\n"); in msm_gpio_init()
1059 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) { in msm_gpio_init()
1060 ret = gpiochip_add_pin_range(&pctrl->chip, in msm_gpio_init()
1061 dev_name(pctrl->dev), 0, 0, chip->ngpio); in msm_gpio_init()
1063 dev_err(pctrl->dev, "Failed to add pin range\n"); in msm_gpio_init()
1064 gpiochip_remove(&pctrl->chip); in msm_gpio_init()
1075 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb); in msm_ps_hold_restart() local
1077 writel(0, pctrl->regs[0] + PS_HOLD_OFFSET); in msm_ps_hold_restart()
1089 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) in msm_pinctrl_setup_pm_reset() argument
1092 const struct msm_function *func = pctrl->soc->functions; in msm_pinctrl_setup_pm_reset()
1094 for (i = 0; i < pctrl->soc->nfunctions; i++) in msm_pinctrl_setup_pm_reset()
1096 pctrl->restart_nb.notifier_call = msm_ps_hold_restart; in msm_pinctrl_setup_pm_reset()
1097 pctrl->restart_nb.priority = 128; in msm_pinctrl_setup_pm_reset()
1098 if (register_restart_handler(&pctrl->restart_nb)) in msm_pinctrl_setup_pm_reset()
1099 dev_err(pctrl->dev, in msm_pinctrl_setup_pm_reset()
1101 poweroff_pctrl = pctrl; in msm_pinctrl_setup_pm_reset()
1109 struct msm_pinctrl *pctrl = dev_get_drvdata(dev); in msm_pinctrl_suspend() local
1111 return pinctrl_force_sleep(pctrl->pctrl); in msm_pinctrl_suspend()
1116 struct msm_pinctrl *pctrl = dev_get_drvdata(dev); in msm_pinctrl_resume() local
1118 return pinctrl_force_default(pctrl->pctrl); in msm_pinctrl_resume()
1129 struct msm_pinctrl *pctrl; in msm_pinctrl_probe() local
1134 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in msm_pinctrl_probe()
1135 if (!pctrl) in msm_pinctrl_probe()
1138 pctrl->dev = &pdev->dev; in msm_pinctrl_probe()
1139 pctrl->soc = soc_data; in msm_pinctrl_probe()
1140 pctrl->chip = msm_gpio_template; in msm_pinctrl_probe()
1142 raw_spin_lock_init(&pctrl->lock); in msm_pinctrl_probe()
1148 pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res); in msm_pinctrl_probe()
1149 if (IS_ERR(pctrl->regs[i])) in msm_pinctrl_probe()
1150 return PTR_ERR(pctrl->regs[i]); in msm_pinctrl_probe()
1154 pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res); in msm_pinctrl_probe()
1155 if (IS_ERR(pctrl->regs[0])) in msm_pinctrl_probe()
1156 return PTR_ERR(pctrl->regs[0]); in msm_pinctrl_probe()
1159 msm_pinctrl_setup_pm_reset(pctrl); in msm_pinctrl_probe()
1161 pctrl->irq = platform_get_irq(pdev, 0); in msm_pinctrl_probe()
1162 if (pctrl->irq < 0) in msm_pinctrl_probe()
1163 return pctrl->irq; in msm_pinctrl_probe()
1165 pctrl->desc.owner = THIS_MODULE; in msm_pinctrl_probe()
1166 pctrl->desc.pctlops = &msm_pinctrl_ops; in msm_pinctrl_probe()
1167 pctrl->desc.pmxops = &msm_pinmux_ops; in msm_pinctrl_probe()
1168 pctrl->desc.confops = &msm_pinconf_ops; in msm_pinctrl_probe()
1169 pctrl->desc.name = dev_name(&pdev->dev); in msm_pinctrl_probe()
1170 pctrl->desc.pins = pctrl->soc->pins; in msm_pinctrl_probe()
1171 pctrl->desc.npins = pctrl->soc->npins; in msm_pinctrl_probe()
1173 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); in msm_pinctrl_probe()
1174 if (IS_ERR(pctrl->pctrl)) { in msm_pinctrl_probe()
1176 return PTR_ERR(pctrl->pctrl); in msm_pinctrl_probe()
1179 ret = msm_gpio_init(pctrl); in msm_pinctrl_probe()
1183 platform_set_drvdata(pdev, pctrl); in msm_pinctrl_probe()
1193 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); in msm_pinctrl_remove() local
1195 gpiochip_remove(&pctrl->chip); in msm_pinctrl_remove()
1197 unregister_restart_handler(&pctrl->restart_nb); in msm_pinctrl_remove()