Lines Matching full:g
71 const struct msm_pingroup *g) \
73 return readl(pctrl->regs[g->tile] + g->name##_reg); \
76 const struct msm_pingroup *g) \
78 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
162 const struct msm_pingroup *g; in msm_pinmux_set_mux() local
167 g = &pctrl->soc->groups[group]; in msm_pinmux_set_mux()
168 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit); in msm_pinmux_set_mux()
170 for (i = 0; i < g->nfuncs; i++) { in msm_pinmux_set_mux()
171 if (g->funcs[i] == function) in msm_pinmux_set_mux()
175 if (WARN_ON(i == g->nfuncs)) in msm_pinmux_set_mux()
180 val = msm_readl_ctl(pctrl, g); in msm_pinmux_set_mux()
182 val |= i << g->mux_bit; in msm_pinmux_set_mux()
183 msm_writel_ctl(val, pctrl, g); in msm_pinmux_set_mux()
195 const struct msm_pingroup *g = &pctrl->soc->groups[offset]; in msm_pinmux_request_gpio() local
198 if (!g->nfuncs) in msm_pinmux_request_gpio()
202 return msm_pinmux_set_mux(pctldev, g->funcs[0], offset); in msm_pinmux_request_gpio()
215 const struct msm_pingroup *g, in msm_config_reg() argument
225 *bit = g->pull_bit; in msm_config_reg()
229 *bit = g->drv_bit; in msm_config_reg()
234 *bit = g->oe_bit; in msm_config_reg()
259 const struct msm_pingroup *g; in msm_config_group_get() local
268 g = &pctrl->soc->groups[group]; in msm_config_group_get()
270 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_get()
274 val = msm_readl_ctl(pctrl, g); in msm_config_group_get()
313 val = msm_readl_io(pctrl, g); in msm_config_group_get()
314 arg = !!(val & BIT(g->in_bit)); in msm_config_group_get()
336 const struct msm_pingroup *g; in msm_config_group_set() local
347 g = &pctrl->soc->groups[group]; in msm_config_group_set()
353 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_set()
387 val = msm_readl_io(pctrl, g); in msm_config_group_set()
389 val |= BIT(g->out_bit); in msm_config_group_set()
391 val &= ~BIT(g->out_bit); in msm_config_group_set()
392 msm_writel_io(val, pctrl, g); in msm_config_group_set()
415 val = msm_readl_ctl(pctrl, g); in msm_config_group_set()
418 msm_writel_ctl(val, pctrl, g); in msm_config_group_set()
433 const struct msm_pingroup *g; in msm_gpio_direction_input() local
438 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_input()
442 val = msm_readl_ctl(pctrl, g); in msm_gpio_direction_input()
443 val &= ~BIT(g->oe_bit); in msm_gpio_direction_input()
444 msm_writel_ctl(val, pctrl, g); in msm_gpio_direction_input()
453 const struct msm_pingroup *g; in msm_gpio_direction_output() local
458 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_output()
462 val = msm_readl_io(pctrl, g); in msm_gpio_direction_output()
464 val |= BIT(g->out_bit); in msm_gpio_direction_output()
466 val &= ~BIT(g->out_bit); in msm_gpio_direction_output()
467 msm_writel_io(val, pctrl, g); in msm_gpio_direction_output()
469 val = msm_readl_ctl(pctrl, g); in msm_gpio_direction_output()
470 val |= BIT(g->oe_bit); in msm_gpio_direction_output()
471 msm_writel_ctl(val, pctrl, g); in msm_gpio_direction_output()
481 const struct msm_pingroup *g; in msm_gpio_get_direction() local
484 g = &pctrl->soc->groups[offset]; in msm_gpio_get_direction()
486 val = msm_readl_ctl(pctrl, g); in msm_gpio_get_direction()
489 return val & BIT(g->oe_bit) ? 0 : 1; in msm_gpio_get_direction()
494 const struct msm_pingroup *g; in msm_gpio_get() local
498 g = &pctrl->soc->groups[offset]; in msm_gpio_get()
500 val = msm_readl_io(pctrl, g); in msm_gpio_get()
501 return !!(val & BIT(g->in_bit)); in msm_gpio_get()
506 const struct msm_pingroup *g; in msm_gpio_set() local
511 g = &pctrl->soc->groups[offset]; in msm_gpio_set()
515 val = msm_readl_io(pctrl, g); in msm_gpio_set()
517 val |= BIT(g->out_bit); in msm_gpio_set()
519 val &= ~BIT(g->out_bit); in msm_gpio_set()
520 msm_writel_io(val, pctrl, g); in msm_gpio_set()
534 const struct msm_pingroup *g; in msm_gpio_dbg_show_one() local
559 g = &pctrl->soc->groups[offset]; in msm_gpio_dbg_show_one()
560 ctl_reg = msm_readl_ctl(pctrl, g); in msm_gpio_dbg_show_one()
561 io_reg = msm_readl_io(pctrl, g); in msm_gpio_dbg_show_one()
563 is_out = !!(ctl_reg & BIT(g->oe_bit)); in msm_gpio_dbg_show_one()
564 func = (ctl_reg >> g->mux_bit) & 7; in msm_gpio_dbg_show_one()
565 drive = (ctl_reg >> g->drv_bit) & 7; in msm_gpio_dbg_show_one()
566 pull = (ctl_reg >> g->pull_bit) & 3; in msm_gpio_dbg_show_one()
569 val = !!(io_reg & BIT(g->out_bit)); in msm_gpio_dbg_show_one()
571 val = !!(io_reg & BIT(g->in_bit)); in msm_gpio_dbg_show_one()
573 seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in"); in msm_gpio_dbg_show_one()
679 const struct msm_pingroup *g, in msm_gpio_update_dual_edge_pos() argument
687 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
689 pol = msm_readl_intr_cfg(pctrl, g); in msm_gpio_update_dual_edge_pos()
690 pol ^= BIT(g->intr_polarity_bit); in msm_gpio_update_dual_edge_pos()
691 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_update_dual_edge_pos()
693 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
694 intstat = msm_readl_intr_status(pctrl, g); in msm_gpio_update_dual_edge_pos()
706 const struct msm_pingroup *g; in msm_gpio_irq_mask() local
710 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_mask()
714 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_mask()
736 val &= ~BIT(g->intr_raw_status_bit); in msm_gpio_irq_mask()
738 val &= ~BIT(g->intr_enable_bit); in msm_gpio_irq_mask()
739 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_mask()
750 const struct msm_pingroup *g; in msm_gpio_irq_clear_unmask() local
754 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_clear_unmask()
764 val = msm_readl_intr_status(pctrl, g); in msm_gpio_irq_clear_unmask()
765 val &= ~BIT(g->intr_status_bit); in msm_gpio_irq_clear_unmask()
766 msm_writel_intr_status(val, pctrl, g); in msm_gpio_irq_clear_unmask()
769 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_clear_unmask()
770 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_clear_unmask()
771 val |= BIT(g->intr_enable_bit); in msm_gpio_irq_clear_unmask()
772 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_clear_unmask()
794 const struct msm_pingroup *g; in msm_gpio_irq_ack() local
798 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_ack()
802 val = msm_readl_intr_status(pctrl, g); in msm_gpio_irq_ack()
803 if (g->intr_ack_high) in msm_gpio_irq_ack()
804 val |= BIT(g->intr_status_bit); in msm_gpio_irq_ack()
806 val &= ~BIT(g->intr_status_bit); in msm_gpio_irq_ack()
807 msm_writel_intr_status(val, pctrl, g); in msm_gpio_irq_ack()
810 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_ack()
819 const struct msm_pingroup *g; in msm_gpio_irq_set_type() local
823 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_set_type()
830 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) in msm_gpio_irq_set_type()
836 val = msm_readl_intr_target(pctrl, g); in msm_gpio_irq_set_type()
837 val &= ~(7 << g->intr_target_bit); in msm_gpio_irq_set_type()
838 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
839 msm_writel_intr_target(val, pctrl, g); in msm_gpio_irq_set_type()
846 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_set_type()
847 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_set_type()
848 if (g->intr_detection_width == 2) { in msm_gpio_irq_set_type()
849 val &= ~(3 << g->intr_detection_bit); in msm_gpio_irq_set_type()
850 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
853 val |= 1 << g->intr_detection_bit; in msm_gpio_irq_set_type()
854 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
857 val |= 2 << g->intr_detection_bit; in msm_gpio_irq_set_type()
858 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
861 val |= 3 << g->intr_detection_bit; in msm_gpio_irq_set_type()
862 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
867 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
870 } else if (g->intr_detection_width == 1) { in msm_gpio_irq_set_type()
871 val &= ~(1 << g->intr_detection_bit); in msm_gpio_irq_set_type()
872 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
875 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
876 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
879 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
882 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
883 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
888 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
894 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_set_type()
897 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_set_type()
962 const struct msm_pingroup *g; in msm_gpio_irq_handler() local
977 g = &pctrl->soc->groups[i]; in msm_gpio_irq_handler()
978 val = msm_readl_intr_status(pctrl, g); in msm_gpio_irq_handler()
979 if (val & BIT(g->intr_status_bit)) { in msm_gpio_irq_handler()