394 static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy)  in qusb2_phy_override_phy_params()  argument
396 	const struct qusb2_phy_cfg *cfg = qphy->cfg;  in qusb2_phy_override_phy_params()
398 	if (qphy->override_imp_res_offset)  in qusb2_phy_override_phy_params()
399 		qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1,  in qusb2_phy_override_phy_params()
400 			     qphy->imp_res_offset_value << IMP_RES_OFFSET_SHIFT,  in qusb2_phy_override_phy_params()
403 	if (qphy->override_hstx_trim)  in qusb2_phy_override_phy_params()
404 		qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],  in qusb2_phy_override_phy_params()
405 				 qphy->hstx_trim_value << HSTX_TRIM_SHIFT,  in qusb2_phy_override_phy_params()
408 	if (qphy->override_preemphasis)  in qusb2_phy_override_phy_params()
409 		qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],  in qusb2_phy_override_phy_params()
410 				qphy->preemphasis_level << PREEMPHASIS_EN_SHIFT,  in qusb2_phy_override_phy_params()
413 	if (qphy->override_preemphasis_width) {  in qusb2_phy_override_phy_params()
414 		if (qphy->preemphasis_width ==  in qusb2_phy_override_phy_params()
416 			qusb2_setbits(qphy->base,  in qusb2_phy_override_phy_params()
420 			qusb2_clrbits(qphy->base,  in qusb2_phy_override_phy_params()
431 static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)  in qusb2_phy_set_tune2_param()  argument
433 	struct device *dev = &qphy->phy->dev;  in qusb2_phy_set_tune2_param()
434 	const struct qusb2_phy_cfg *cfg = qphy->cfg;  in qusb2_phy_set_tune2_param()
438 	if (!qphy->cell)  in qusb2_phy_set_tune2_param()
448 	val = nvmem_cell_read(qphy->cell, NULL);  in qusb2_phy_set_tune2_param()
456 		qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],  in qusb2_phy_set_tune2_param()
460 		qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],  in qusb2_phy_set_tune2_param()
468 	struct qusb2_phy *qphy = phy_get_drvdata(phy);  in qusb2_phy_set_mode()  local
470 	qphy->mode = mode;  in qusb2_phy_set_mode()
477 	struct qusb2_phy *qphy = dev_get_drvdata(dev);  in qusb2_phy_runtime_suspend()  local
478 	const struct qusb2_phy_cfg *cfg = qphy->cfg;  in qusb2_phy_runtime_suspend()
481 	dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode);  in qusb2_phy_runtime_suspend()
483 	if (!qphy->phy_initialized) {  in qusb2_phy_runtime_suspend()
495 	switch (qphy->mode) {  in qusb2_phy_runtime_suspend()
513 	writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);  in qusb2_phy_runtime_suspend()
517 		qusb2_setbits(qphy->base,  in qusb2_phy_runtime_suspend()
524 	if (qphy->mode != PHY_MODE_INVALID) {  in qusb2_phy_runtime_suspend()
525 		qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],  in qusb2_phy_runtime_suspend()
528 		qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],  in qusb2_phy_runtime_suspend()
532 	if (!qphy->has_se_clk_scheme)  in qusb2_phy_runtime_suspend()
533 		clk_disable_unprepare(qphy->ref_clk);  in qusb2_phy_runtime_suspend()
535 	clk_disable_unprepare(qphy->cfg_ahb_clk);  in qusb2_phy_runtime_suspend()
536 	clk_disable_unprepare(qphy->iface_clk);  in qusb2_phy_runtime_suspend()
543 	struct qusb2_phy *qphy = dev_get_drvdata(dev);  in qusb2_phy_runtime_resume()  local
544 	const struct qusb2_phy_cfg *cfg = qphy->cfg;  in qusb2_phy_runtime_resume()
547 	dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode);  in qusb2_phy_runtime_resume()
549 	if (!qphy->phy_initialized) {  in qusb2_phy_runtime_resume()
554 	ret = clk_prepare_enable(qphy->iface_clk);  in qusb2_phy_runtime_resume()
560 	ret = clk_prepare_enable(qphy->cfg_ahb_clk);  in qusb2_phy_runtime_resume()
566 	if (!qphy->has_se_clk_scheme) {  in qusb2_phy_runtime_resume()
567 		ret = clk_prepare_enable(qphy->ref_clk);  in qusb2_phy_runtime_resume()
574 	writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);  in qusb2_phy_runtime_resume()
578 		qusb2_clrbits(qphy->base,  in qusb2_phy_runtime_resume()
586 	clk_disable_unprepare(qphy->cfg_ahb_clk);  in qusb2_phy_runtime_resume()
588 	clk_disable_unprepare(qphy->iface_clk);  in qusb2_phy_runtime_resume()
595 	struct qusb2_phy *qphy = phy_get_drvdata(phy);  in qusb2_phy_init()  local
596 	const struct qusb2_phy_cfg *cfg = qphy->cfg;  in qusb2_phy_init()
604 	ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs);  in qusb2_phy_init()
608 	ret = clk_prepare_enable(qphy->iface_clk);  in qusb2_phy_init()
615 	ret = clk_prepare_enable(qphy->cfg_ahb_clk);  in qusb2_phy_init()
622 	ret = reset_control_assert(qphy->phy_reset);  in qusb2_phy_init()
631 	ret = reset_control_deassert(qphy->phy_reset);  in qusb2_phy_init()
638 	qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],  in qusb2_phy_init()
639 		      qphy->cfg->disable_ctrl);  in qusb2_phy_init()
643 		val = readl(qphy->base + QUSB2PHY_PLL_TEST);  in qusb2_phy_init()
646 	qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl,  in qusb2_phy_init()
650 	qusb2_phy_override_phy_params(qphy);  in qusb2_phy_init()
653 	qusb2_phy_set_tune2_param(qphy);  in qusb2_phy_init()
656 	qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],  in qusb2_phy_init()
663 	qphy->has_se_clk_scheme = true;  in qusb2_phy_init()
670 	if (qphy->tcsr) {  in qusb2_phy_init()
671 		ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset,  in qusb2_phy_init()
682 			qphy->has_se_clk_scheme = false;  in qusb2_phy_init()
689 	if (!qphy->has_se_clk_scheme) {  in qusb2_phy_init()
690 		ret = clk_prepare_enable(qphy->ref_clk);  in qusb2_phy_init()
699 		if (!qphy->has_se_clk_scheme)  in qusb2_phy_init()
704 		writel(val, qphy->base + QUSB2PHY_PLL_TEST);  in qusb2_phy_init()
707 		readl(qphy->base + QUSB2PHY_PLL_TEST);  in qusb2_phy_init()
713 	val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]);  in qusb2_phy_init()
720 	qphy->phy_initialized = true;  in qusb2_phy_init()
725 	if (!qphy->has_se_clk_scheme)  in qusb2_phy_init()
726 		clk_disable_unprepare(qphy->ref_clk);  in qusb2_phy_init()
728 	reset_control_assert(qphy->phy_reset);  in qusb2_phy_init()
730 	clk_disable_unprepare(qphy->cfg_ahb_clk);  in qusb2_phy_init()
732 	clk_disable_unprepare(qphy->iface_clk);  in qusb2_phy_init()
734 	regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);  in qusb2_phy_init()
741 	struct qusb2_phy *qphy = phy_get_drvdata(phy);  in qusb2_phy_exit()  local
744 	qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN],  in qusb2_phy_exit()
745 		      qphy->cfg->disable_ctrl);  in qusb2_phy_exit()
747 	if (!qphy->has_se_clk_scheme)  in qusb2_phy_exit()
748 		clk_disable_unprepare(qphy->ref_clk);  in qusb2_phy_exit()
750 	reset_control_assert(qphy->phy_reset);  in qusb2_phy_exit()
752 	clk_disable_unprepare(qphy->cfg_ahb_clk);  in qusb2_phy_exit()
753 	clk_disable_unprepare(qphy->iface_clk);  in qusb2_phy_exit()
755 	regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);  in qusb2_phy_exit()
757 	qphy->phy_initialized = false;  in qusb2_phy_exit()
792 	struct qusb2_phy *qphy;  in qusb2_phy_probe()  local
800 	qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);  in qusb2_phy_probe()
801 	if (!qphy)  in qusb2_phy_probe()
805 	qphy->base = devm_ioremap_resource(dev, res);  in qusb2_phy_probe()
806 	if (IS_ERR(qphy->base))  in qusb2_phy_probe()
807 		return PTR_ERR(qphy->base);  in qusb2_phy_probe()
809 	qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb");  in qusb2_phy_probe()
810 	if (IS_ERR(qphy->cfg_ahb_clk)) {  in qusb2_phy_probe()
811 		ret = PTR_ERR(qphy->cfg_ahb_clk);  in qusb2_phy_probe()
817 	qphy->ref_clk = devm_clk_get(dev, "ref");  in qusb2_phy_probe()
818 	if (IS_ERR(qphy->ref_clk)) {  in qusb2_phy_probe()
819 		ret = PTR_ERR(qphy->ref_clk);  in qusb2_phy_probe()
825 	qphy->iface_clk = devm_clk_get_optional(dev, "iface");  in qusb2_phy_probe()
826 	if (IS_ERR(qphy->iface_clk))  in qusb2_phy_probe()
827 		return PTR_ERR(qphy->iface_clk);  in qusb2_phy_probe()
829 	qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0);  in qusb2_phy_probe()
830 	if (IS_ERR(qphy->phy_reset)) {  in qusb2_phy_probe()
832 		return PTR_ERR(qphy->phy_reset);  in qusb2_phy_probe()
835 	num = ARRAY_SIZE(qphy->vregs);  in qusb2_phy_probe()
837 		qphy->vregs[i].supply = qusb2_phy_vreg_names[i];  in qusb2_phy_probe()
839 	ret = devm_regulator_bulk_get(dev, num, qphy->vregs);  in qusb2_phy_probe()
848 	qphy->cfg = of_device_get_match_data(dev);  in qusb2_phy_probe()
850 	qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node,  in qusb2_phy_probe()
852 	if (IS_ERR(qphy->tcsr)) {  in qusb2_phy_probe()
854 		qphy->tcsr = NULL;  in qusb2_phy_probe()
857 	qphy->cell = devm_nvmem_cell_get(dev, NULL);  in qusb2_phy_probe()
858 	if (IS_ERR(qphy->cell)) {  in qusb2_phy_probe()
859 		if (PTR_ERR(qphy->cell) == -EPROBE_DEFER)  in qusb2_phy_probe()
861 		qphy->cell = NULL;  in qusb2_phy_probe()
867 		qphy->imp_res_offset_value = (u8)value;  in qusb2_phy_probe()
868 		qphy->override_imp_res_offset = true;  in qusb2_phy_probe()
873 		qphy->hstx_trim_value = (u8)value;  in qusb2_phy_probe()
874 		qphy->override_hstx_trim = true;  in qusb2_phy_probe()
879 		qphy->preemphasis_level = (u8)value;  in qusb2_phy_probe()
880 		qphy->override_preemphasis = true;  in qusb2_phy_probe()
885 		qphy->preemphasis_width = (u8)value;  in qusb2_phy_probe()
886 		qphy->override_preemphasis_width = true;  in qusb2_phy_probe()
904 	qphy->phy = generic_phy;  in qusb2_phy_probe()
906 	dev_set_drvdata(dev, qphy);  in qusb2_phy_probe()
907 	phy_set_drvdata(generic_phy, qphy);  in qusb2_phy_probe()