93 	struct hw_pmu_info *inf;  member
142 	struct hw_pmu_info inf;  member
737 	return readl(pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));  in xgene_pmu_read_counter32()
762 	writel(val, pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));  in xgene_pmu_write_counter32()
781 	writel(val, pmu_dev->inf->csr + PMU_PMEVTYPER0 + (4 * idx));  in xgene_pmu_write_evttype()
787 	writel(val, pmu_dev->inf->csr + PMU_PMAMR0);  in xgene_pmu_write_agentmsk()
796 	writel(val, pmu_dev->inf->csr + PMU_PMAMR1);  in xgene_pmu_write_agent1msk()
807 	val = readl(pmu_dev->inf->csr + PMU_PMCNTENSET);  in xgene_pmu_enable_counter()
809 	writel(val, pmu_dev->inf->csr + PMU_PMCNTENSET);  in xgene_pmu_enable_counter()
817 	val = readl(pmu_dev->inf->csr + PMU_PMCNTENCLR);  in xgene_pmu_disable_counter()
819 	writel(val, pmu_dev->inf->csr + PMU_PMCNTENCLR);  in xgene_pmu_disable_counter()
827 	val = readl(pmu_dev->inf->csr + PMU_PMINTENSET);  in xgene_pmu_enable_counter_int()
829 	writel(val, pmu_dev->inf->csr + PMU_PMINTENSET);  in xgene_pmu_enable_counter_int()
837 	val = readl(pmu_dev->inf->csr + PMU_PMINTENCLR);  in xgene_pmu_disable_counter_int()
839 	writel(val, pmu_dev->inf->csr + PMU_PMINTENCLR);  in xgene_pmu_disable_counter_int()
846 	val = readl(pmu_dev->inf->csr + PMU_PMCR);  in xgene_pmu_reset_counters()
848 	writel(val, pmu_dev->inf->csr + PMU_PMCR);  in xgene_pmu_reset_counters()
855 	val = readl(pmu_dev->inf->csr + PMU_PMCR);  in xgene_pmu_start_counters()
857 	writel(val, pmu_dev->inf->csr + PMU_PMCR);  in xgene_pmu_start_counters()
864 	val = readl(pmu_dev->inf->csr + PMU_PMCR);  in xgene_pmu_stop_counters()
866 	writel(val, pmu_dev->inf->csr + PMU_PMCR);  in xgene_pmu_stop_counters()
955 	if (pmu_dev->inf->type == PMU_TYPE_IOB)  in xgene_perf_enable_event()
1140 	pmu->inf = &ctx->inf;  in xgene_pmu_dev_add()
1143 	switch (pmu->inf->type) {  in xgene_pmu_dev_add()
1145 		if (!(xgene_pmu->l3c_active_mask & pmu->inf->enable_mask))  in xgene_pmu_dev_add()
1163 		if (!(xgene_pmu->mcb_active_mask & pmu->inf->enable_mask))  in xgene_pmu_dev_add()
1171 		if (!(xgene_pmu->mc_active_mask & pmu->inf->enable_mask))  in xgene_pmu_dev_add()
1195 	void __iomem *csr = pmu_dev->inf->csr;  in _xgene_pmu_isr()
1481 	struct hw_pmu_info *inf;  in acpi_get_pmu_hw_inf()  local
1519 	inf = &ctx->inf;  in acpi_get_pmu_hw_inf()
1520 	inf->type = type;  in acpi_get_pmu_hw_inf()
1521 	inf->csr = dev_csr;  in acpi_get_pmu_hw_inf()
1522 	inf->enable_mask = 1 << enable_bit;  in acpi_get_pmu_hw_inf()
1584 	switch (ctx->inf.type) {  in acpi_pmu_dev_add()
1638 	struct hw_pmu_info *inf;  in fdt_get_pmu_hw_inf()  local
1668 	inf = &ctx->inf;  in fdt_get_pmu_hw_inf()
1669 	inf->type = type;  in fdt_get_pmu_hw_inf()
1670 	inf->csr = dev_csr;  in fdt_get_pmu_hw_inf()
1671 	inf->enable_mask = 1 << enable_bit;  in fdt_get_pmu_hw_inf()
1706 		switch (ctx->inf.type) {  in fdt_pmu_probe_pmu_dev()