120 #define CCN_NUM_XP_WATCHPOINTS		2 /* See DT.dbg_id.num_watchpoints */
121 #define CCN_NUM_PMU_EVENT_COUNTERS	8 /* See DT.dbg_id.num_pmucntr */
143 	struct arm_ccn_dt, pmu), struct arm_ccn, dt)
183 	struct arm_ccn_dt dt;  member
465 		return &ccn->dt.cmp_mask[i].l;  in arm_ccn_pmu_get_cmp_mask()
467 		return &ccn->dt.cmp_mask[i].h;  in arm_ccn_pmu_get_cmp_mask()
555 	return cpumap_print_to_pagebuf(true, buf, cpumask_of(ccn->dt.cpu));  in arm_ccn_pmu_cpumask_show()
651 				ccn->dt.pmu_counters_mask))  in arm_ccn_pmu_event_alloc()
655 		ccn->dt.pmu_counters[CCN_IDX_PMU_CYCLE_COUNTER].event = event;  in arm_ccn_pmu_event_alloc()
661 	hw->idx = arm_ccn_pmu_alloc_bit(ccn->dt.pmu_counters_mask,  in arm_ccn_pmu_event_alloc()
672 	ccn->dt.pmu_counters[hw->idx].source = source;  in arm_ccn_pmu_event_alloc()
684 		clear_bit(hw->idx, ccn->dt.pmu_counters_mask);  in arm_ccn_pmu_event_alloc()
689 	ccn->dt.pmu_counters[hw->idx].event = event;  in arm_ccn_pmu_event_alloc()
700 		clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask);  in arm_ccn_pmu_event_release()
703 				ccn->dt.pmu_counters[hw->idx].source;  in arm_ccn_pmu_event_release()
711 		clear_bit(hw->idx, ccn->dt.pmu_counters_mask);  in arm_ccn_pmu_event_release()
714 	ccn->dt.pmu_counters[hw->idx].source = NULL;  in arm_ccn_pmu_event_release()
715 	ccn->dt.pmu_counters[hw->idx].event = NULL;  in arm_ccn_pmu_event_release()
755 	event->cpu = ccn->dt.cpu;  in arm_ccn_pmu_event_init()
855 		res = readq(ccn->dt.base + CCN_DT_PMCCNTR);  in arm_ccn_pmu_read_counter()
858 		writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ);  in arm_ccn_pmu_read_counter()
859 		while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1))  in arm_ccn_pmu_read_counter()
861 		writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);  in arm_ccn_pmu_read_counter()
862 		res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff;  in arm_ccn_pmu_read_counter()
864 		res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR);  in arm_ccn_pmu_read_counter()
867 		res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx));  in arm_ccn_pmu_read_counter()
911 	spin_lock(&ccn->dt.config_lock);  in arm_ccn_pmu_xp_dt_config()
919 	spin_unlock(&ccn->dt.config_lock);  in arm_ccn_pmu_xp_dt_config()
931 	/* Set the DT bus input, engaging the counter */  in arm_ccn_pmu_event_start()
939 	/* Disable counting, setting the DT bus to pass-through mode */  in arm_ccn_pmu_event_stop()
953 			ccn->dt.pmu_counters[hw->idx].source;  in arm_ccn_pmu_xp_watchpoint_config()
958 	u64 mask_l = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].l;  in arm_ccn_pmu_xp_watchpoint_config()
959 	u64 mask_h = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].h;  in arm_ccn_pmu_xp_watchpoint_config()
1001 			ccn->dt.pmu_counters[hw->idx].source;  in arm_ccn_pmu_xp_event_config()
1022 			ccn->dt.pmu_counters[hw->idx].source;  in arm_ccn_pmu_node_event_config()
1069 	spin_lock(&ccn->dt.config_lock);  in arm_ccn_pmu_event_config()
1071 	/* Set the DT bus "distance" register */  in arm_ccn_pmu_event_config()
1073 	val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);  in arm_ccn_pmu_event_config()
1077 	writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);  in arm_ccn_pmu_event_config()
1089 	spin_unlock(&ccn->dt.config_lock);  in arm_ccn_pmu_event_config()
1094 	return bitmap_weight(ccn->dt.pmu_counters_mask,  in arm_ccn_pmu_active_counters()
1114 		hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(),  in arm_ccn_pmu_event_add()
1136 		hrtimer_cancel(&ccn->dt.hrtimer);  in arm_ccn_pmu_event_del()
1148 	u32 val = readl(ccn->dt.base + CCN_DT_PMCR);  in arm_ccn_pmu_enable()
1150 	writel(val, ccn->dt.base + CCN_DT_PMCR);  in arm_ccn_pmu_enable()
1157 	u32 val = readl(ccn->dt.base + CCN_DT_PMCR);  in arm_ccn_pmu_disable()
1159 	writel(val, ccn->dt.base + CCN_DT_PMCR);  in arm_ccn_pmu_disable()
1162 static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt)  in arm_ccn_pmu_overflow_handler()  argument
1164 	u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR);  in arm_ccn_pmu_overflow_handler()
1170 	writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR);  in arm_ccn_pmu_overflow_handler()
1175 		struct perf_event *event = dt->pmu_counters[idx].event;  in arm_ccn_pmu_overflow_handler()
1192 	struct arm_ccn_dt *dt = container_of(hrtimer, struct arm_ccn_dt,  in arm_ccn_pmu_timer_handler()  local
1197 	arm_ccn_pmu_overflow_handler(dt);  in arm_ccn_pmu_timer_handler()
1207 	struct arm_ccn_dt *dt = hlist_entry_safe(node, struct arm_ccn_dt, node);  in arm_ccn_pmu_offline_cpu()  local
1208 	struct arm_ccn *ccn = container_of(dt, struct arm_ccn, dt);  in arm_ccn_pmu_offline_cpu()
1211 	if (cpu != dt->cpu)  in arm_ccn_pmu_offline_cpu()
1216 	perf_pmu_migrate_context(&dt->pmu, cpu, target);  in arm_ccn_pmu_offline_cpu()
1217 	dt->cpu = target;  in arm_ccn_pmu_offline_cpu()
1219 		WARN_ON(irq_set_affinity_hint(ccn->irq, cpumask_of(dt->cpu)));  in arm_ccn_pmu_offline_cpu()
1231 	/* Initialize DT subsystem */  in arm_ccn_pmu_init()
1232 	ccn->dt.base = ccn->base + CCN_REGION_SIZE;  in arm_ccn_pmu_init()
1233 	spin_lock_init(&ccn->dt.config_lock);  in arm_ccn_pmu_init()
1234 	writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR);  in arm_ccn_pmu_init()
1235 	writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL);  in arm_ccn_pmu_init()
1237 			ccn->dt.base + CCN_DT_PMCR);  in arm_ccn_pmu_init()
1238 	writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);  in arm_ccn_pmu_init()
1248 	ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].l = ~0;  in arm_ccn_pmu_init()
1249 	ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].h = ~0;  in arm_ccn_pmu_init()
1250 	ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].l = 0;  in arm_ccn_pmu_init()
1251 	ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].h = 0;  in arm_ccn_pmu_init()
1252 	ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].l = ~0;  in arm_ccn_pmu_init()
1253 	ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].h = ~(0x1 << 15);  in arm_ccn_pmu_init()
1254 	ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].l = ~0;  in arm_ccn_pmu_init()
1255 	ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].h = ~(0x1f << 9);  in arm_ccn_pmu_init()
1258 	ccn->dt.id = ida_simple_get(&arm_ccn_pmu_ida, 0, 0, GFP_KERNEL);  in arm_ccn_pmu_init()
1259 	if (ccn->dt.id == 0) {  in arm_ccn_pmu_init()
1263 				      ccn->dt.id);  in arm_ccn_pmu_init()
1271 	ccn->dt.pmu = (struct pmu) {  in arm_ccn_pmu_init()
1289 		hrtimer_init(&ccn->dt.hrtimer, CLOCK_MONOTONIC,  in arm_ccn_pmu_init()
1291 		ccn->dt.hrtimer.function = arm_ccn_pmu_timer_handler;  in arm_ccn_pmu_init()
1295 	ccn->dt.cpu = raw_smp_processor_id();  in arm_ccn_pmu_init()
1299 		err = irq_set_affinity_hint(ccn->irq, cpumask_of(ccn->dt.cpu));  in arm_ccn_pmu_init()
1307 					 &ccn->dt.node);  in arm_ccn_pmu_init()
1309 	err = perf_pmu_register(&ccn->dt.pmu, name, -1);  in arm_ccn_pmu_init()
1317 					    &ccn->dt.node);  in arm_ccn_pmu_init()
1320 	ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id);  in arm_ccn_pmu_init()
1323 	writel(0, ccn->dt.base + CCN_DT_PMCR);  in arm_ccn_pmu_init()
1332 					    &ccn->dt.node);  in arm_ccn_pmu_cleanup()
1337 	writel(0, ccn->dt.base + CCN_DT_PMCR);  in arm_ccn_pmu_cleanup()
1338 	perf_pmu_unregister(&ccn->dt.pmu);  in arm_ccn_pmu_cleanup()
1339 	ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id);  in arm_ccn_pmu_cleanup()
1447 		res = arm_ccn_pmu_overflow_handler(&ccn->dt);  in arm_ccn_irq_handler()