147 	pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);  in enable_ecrc_checking()
175 	pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);  in disable_ecrc_checking()
390 	pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);  in pci_cleanup_aer_uncorrect_error_status()
391 	pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &sev);  in pci_cleanup_aer_uncorrect_error_status()
413 	pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);  in pci_aer_clear_fatal_status()
414 	pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &sev);  in pci_aer_clear_fatal_status()
438 		pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &status);  in pci_cleanup_aer_error_status_regs()
442 	pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &status);  in pci_cleanup_aer_error_status_regs()
445 	pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);  in pci_cleanup_aer_error_status_regs()
911 		pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &status);  in is_error_source()
912 		pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &mask);  in is_error_source()
914 		pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);  in is_error_source()
915 		pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &mask);  in is_error_source()
1101 		pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS,  in aer_get_device_error_info()
1103 		pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK,  in aer_get_device_error_info()
1112 		pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,  in aer_get_device_error_info()
1114 		pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK,  in aer_get_device_error_info()
1120 		pci_read_config_dword(dev, pos + PCI_ERR_CAP, &temp);  in aer_get_device_error_info()
1125 			pci_read_config_dword(dev,  in aer_get_device_error_info()
1127 			pci_read_config_dword(dev,  in aer_get_device_error_info()
1129 			pci_read_config_dword(dev,  in aer_get_device_error_info()
1131 			pci_read_config_dword(dev,  in aer_get_device_error_info()
1240 	pci_read_config_dword(rp, pos + PCI_ERR_ROOT_STATUS, &e_src.status);  in aer_irq()
1244 	pci_read_config_dword(rp, pos + PCI_ERR_ROOT_ERR_SRC, &e_src.id);  in aer_irq()
1311 	pci_read_config_dword(pdev, aer_pos + PCI_ERR_ROOT_STATUS, &reg32);  in aer_enable_rootport()
1313 	pci_read_config_dword(pdev, aer_pos + PCI_ERR_COR_STATUS, &reg32);  in aer_enable_rootport()
1315 	pci_read_config_dword(pdev, aer_pos + PCI_ERR_UNCOR_STATUS, &reg32);  in aer_enable_rootport()
1325 	pci_read_config_dword(pdev, aer_pos + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_enable_rootport()
1350 	pci_read_config_dword(pdev, pos + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_disable_rootport()
1355 	pci_read_config_dword(pdev, pos + PCI_ERR_ROOT_STATUS, &reg32);  in aer_disable_rootport()
1419 	pci_read_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_root_reset()
1427 	pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &reg32);  in aer_root_reset()
1431 	pci_read_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_root_reset()