120 	if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&  in pcie_wait_cmd()
121 	    ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)  in pcie_wait_cmd()
128 			  ctrl->slot_ctrl,  in pcie_wait_cmd()
141 	u16 slot_ctrl_orig, slot_ctrl;  in pcie_do_write_cmd()  local
150 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);  in pcie_do_write_cmd()
151 	if (slot_ctrl == (u16) ~0) {  in pcie_do_write_cmd()
156 	slot_ctrl_orig = slot_ctrl;  in pcie_do_write_cmd()
157 	slot_ctrl &= ~mask;  in pcie_do_write_cmd()
158 	slot_ctrl |= (cmd & mask);  in pcie_do_write_cmd()
161 	ctrl->slot_ctrl = slot_ctrl;  in pcie_do_write_cmd()
162 	pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);  in pcie_do_write_cmd()
173 	    (slot_ctrl_orig & CC_ERRATUM_MASK) == (slot_ctrl & CC_ERRATUM_MASK))  in pcie_do_write_cmd()
306 	u16 slot_ctrl;  in pciehp_get_raw_indicator_status()  local
309 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);  in pciehp_get_raw_indicator_status()
311 	*status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6;  in pciehp_get_raw_indicator_status()
319 	u16 slot_ctrl;  in pciehp_get_attention_status()  local
322 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);  in pciehp_get_attention_status()
325 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);  in pciehp_get_attention_status()
327 	switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {  in pciehp_get_attention_status()
348 	u16 slot_ctrl;  in pciehp_get_power_status()  local
350 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);  in pciehp_get_power_status()
352 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);  in pciehp_get_power_status()
354 	switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {  in pciehp_get_power_status()
502 	    (!(ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE) && !pciehp_poll_mode))  in pciehp_isr()