74 			dev_err(dev, "missing core reset property in node\n");  in rockchip_pcie_parse_dt()
81 			dev_err(dev, "missing mgmt reset property in node\n");  in rockchip_pcie_parse_dt()
89 			dev_err(dev, "missing mgmt-sticky reset property in node\n");  in rockchip_pcie_parse_dt()
96 			dev_err(dev, "missing pipe reset property in node\n");  in rockchip_pcie_parse_dt()
103 			dev_err(dev, "missing pm reset property in node\n");  in rockchip_pcie_parse_dt()
110 			dev_err(dev, "missing pclk reset property in node\n");  in rockchip_pcie_parse_dt()
117 			dev_err(dev, "missing aclk reset property in node\n");  in rockchip_pcie_parse_dt()
124 			dev_err(dev, "missing ep-gpios property in node\n");  in rockchip_pcie_parse_dt()
131 		dev_err(dev, "aclk clock not found\n");  in rockchip_pcie_parse_dt()
137 		dev_err(dev, "aclk_perf clock not found\n");  in rockchip_pcie_parse_dt()
143 		dev_err(dev, "hclk clock not found\n");  in rockchip_pcie_parse_dt()
149 		dev_err(dev, "pm clock not found\n");  in rockchip_pcie_parse_dt()
165 		dev_err(dev, "assert aclk_rst err %d\n", err);  in rockchip_pcie_init_port()
171 		dev_err(dev, "assert pclk_rst err %d\n", err);  in rockchip_pcie_init_port()
177 		dev_err(dev, "assert pm_rst err %d\n", err);  in rockchip_pcie_init_port()
184 			dev_err(dev, "init phy%d err %d\n", i, err);  in rockchip_pcie_init_port()
191 		dev_err(dev, "assert core_rst err %d\n", err);  in rockchip_pcie_init_port()
197 		dev_err(dev, "assert mgmt_rst err %d\n", err);  in rockchip_pcie_init_port()
203 		dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);  in rockchip_pcie_init_port()
209 		dev_err(dev, "assert pipe_rst err %d\n", err);  in rockchip_pcie_init_port()
217 		dev_err(dev, "deassert pm_rst err %d\n", err);  in rockchip_pcie_init_port()
223 		dev_err(dev, "deassert aclk_rst err %d\n", err);  in rockchip_pcie_init_port()
229 		dev_err(dev, "deassert pclk_rst err %d\n", err);  in rockchip_pcie_init_port()
253 			dev_err(dev, "power on phy%d err %d\n", i, err);  in rockchip_pcie_init_port()
264 		dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);  in rockchip_pcie_init_port()
270 		dev_err(dev, "deassert core_rst err %d\n", err);  in rockchip_pcie_init_port()
276 		dev_err(dev, "deassert mgmt_rst err %d\n", err);  in rockchip_pcie_init_port()
282 		dev_err(dev, "deassert pipe_rst err %d\n", err);  in rockchip_pcie_init_port()
328 				dev_err(dev, "missing phy for lane %d: %ld\n",  in rockchip_pcie_get_phys()
360 		dev_err(dev, "unable to enable aclk_pcie clock\n");  in rockchip_pcie_enable_clocks()
366 		dev_err(dev, "unable to enable aclk_perf_pcie clock\n");  in rockchip_pcie_enable_clocks()
372 		dev_err(dev, "unable to enable hclk_pcie clock\n");  in rockchip_pcie_enable_clocks()
378 		dev_err(dev, "unable to enable clk_pcie_pm clock\n");  in rockchip_pcie_enable_clocks()