168 static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx)  in mobiveil_pcie_sel_page()  argument
172 	val = readl(pcie->csr_axi_slave_base + PAB_CTRL);  in mobiveil_pcie_sel_page()
176 	writel(val, pcie->csr_axi_slave_base + PAB_CTRL);  in mobiveil_pcie_sel_page()
179 static void *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, u32 off)  in mobiveil_pcie_comp_addr()  argument
183 		mobiveil_pcie_sel_page(pcie, 0);  in mobiveil_pcie_comp_addr()
184 		return pcie->csr_axi_slave_base + off;  in mobiveil_pcie_comp_addr()
187 	mobiveil_pcie_sel_page(pcie, OFFSET_TO_PAGE_IDX(off));  in mobiveil_pcie_comp_addr()
188 	return pcie->csr_axi_slave_base + OFFSET_TO_PAGE_ADDR(off);  in mobiveil_pcie_comp_addr()
238 static u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size)  in csr_read()  argument
244 	addr = mobiveil_pcie_comp_addr(pcie, off);  in csr_read()
248 		dev_err(&pcie->pdev->dev, "read CSR address failed\n");  in csr_read()
253 static void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size)  in csr_write()  argument
258 	addr = mobiveil_pcie_comp_addr(pcie, off);  in csr_write()
262 		dev_err(&pcie->pdev->dev, "write CSR address failed\n");  in csr_write()
265 static u32 csr_readl(struct mobiveil_pcie *pcie, u32 off)  in csr_readl()  argument
267 	return csr_read(pcie, off, 0x4);  in csr_readl()
270 static void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off)  in csr_writel()  argument
272 	csr_write(pcie, val, off, 0x4);  in csr_writel()
275 static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)  in mobiveil_pcie_link_up()  argument
277 	return (csr_readl(pcie, LTSSM_STATUS) &  in mobiveil_pcie_link_up()
283 	struct mobiveil_pcie *pcie = bus->sysdata;  in mobiveil_pcie_valid_device()  local
286 	if ((bus->number == pcie->root_bus_nr) && (devfn > 0))  in mobiveil_pcie_valid_device()
293 	if ((bus->primary == pcie->root_bus_nr) && (PCI_SLOT(devfn) > 0))  in mobiveil_pcie_valid_device()
306 	struct mobiveil_pcie *pcie = bus->sysdata;  in mobiveil_pcie_map_bus()  local
313 	if (bus->number == pcie->root_bus_nr)  in mobiveil_pcie_map_bus()
314 		return pcie->csr_axi_slave_base + where;  in mobiveil_pcie_map_bus()
326 	csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));  in mobiveil_pcie_map_bus()
328 	return pcie->config_axi_slave_base + where;  in mobiveil_pcie_map_bus()
340 	struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc);  in mobiveil_pcie_isr()  local
341 	struct device *dev = &pcie->pdev->dev;  in mobiveil_pcie_isr()
342 	struct mobiveil_msi *msi = &pcie->msi;  in mobiveil_pcie_isr()
356 	val = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);  in mobiveil_pcie_isr()
357 	mask = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);  in mobiveil_pcie_isr()
362 		shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);  in mobiveil_pcie_isr()
367 				virq = irq_find_mapping(pcie->intx_domain,  in mobiveil_pcie_isr()
376 				csr_writel(pcie, 1 << (PAB_INTX_START + bit),  in mobiveil_pcie_isr()
380 			shifted_status = csr_readl(pcie,  in mobiveil_pcie_isr()
388 	msi_status = readl_relaxed(pcie->apb_csr_base + MSI_STATUS_OFFSET);  in mobiveil_pcie_isr()
392 		msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET);  in mobiveil_pcie_isr()
400 		msi_addr_lo = readl_relaxed(pcie->apb_csr_base +  in mobiveil_pcie_isr()
402 		msi_addr_hi = readl_relaxed(pcie->apb_csr_base +  in mobiveil_pcie_isr()
411 		msi_status = readl_relaxed(pcie->apb_csr_base +  in mobiveil_pcie_isr()
416 	csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT);  in mobiveil_pcie_isr()
420 static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)  in mobiveil_pcie_parse_dt()  argument
422 	struct device *dev = &pcie->pdev->dev;  in mobiveil_pcie_parse_dt()
423 	struct platform_device *pdev = pcie->pdev;  in mobiveil_pcie_parse_dt()
430 	pcie->config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);  in mobiveil_pcie_parse_dt()
431 	if (IS_ERR(pcie->config_axi_slave_base))  in mobiveil_pcie_parse_dt()
432 		return PTR_ERR(pcie->config_axi_slave_base);  in mobiveil_pcie_parse_dt()
433 	pcie->ob_io_res = res;  in mobiveil_pcie_parse_dt()
438 	pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);  in mobiveil_pcie_parse_dt()
439 	if (IS_ERR(pcie->csr_axi_slave_base))  in mobiveil_pcie_parse_dt()
440 		return PTR_ERR(pcie->csr_axi_slave_base);  in mobiveil_pcie_parse_dt()
441 	pcie->pcie_reg_base = res->start;  in mobiveil_pcie_parse_dt()
445 	pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res);  in mobiveil_pcie_parse_dt()
446 	if (IS_ERR(pcie->apb_csr_base))  in mobiveil_pcie_parse_dt()
447 		return PTR_ERR(pcie->apb_csr_base);  in mobiveil_pcie_parse_dt()
450 	if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins))  in mobiveil_pcie_parse_dt()
451 		pcie->apio_wins = MAX_PIO_WINDOWS;  in mobiveil_pcie_parse_dt()
453 	if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins))  in mobiveil_pcie_parse_dt()
454 		pcie->ppio_wins = MAX_PIO_WINDOWS;  in mobiveil_pcie_parse_dt()
456 	pcie->irq = platform_get_irq(pdev, 0);  in mobiveil_pcie_parse_dt()
457 	if (pcie->irq <= 0) {  in mobiveil_pcie_parse_dt()
458 		dev_err(dev, "failed to map IRQ: %d\n", pcie->irq);  in mobiveil_pcie_parse_dt()
465 static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,  in program_ib_windows()  argument
471 	if (win_num >= pcie->ppio_wins) {  in program_ib_windows()
472 		dev_err(&pcie->pdev->dev,  in program_ib_windows()
477 	value = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));  in program_ib_windows()
481 	csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num));  in program_ib_windows()
483 	csr_writel(pcie, upper_32_bits(size64),  in program_ib_windows()
486 	csr_writel(pcie, lower_32_bits(cpu_addr),  in program_ib_windows()
488 	csr_writel(pcie, upper_32_bits(cpu_addr),  in program_ib_windows()
491 	csr_writel(pcie, lower_32_bits(pci_addr),  in program_ib_windows()
493 	csr_writel(pcie, upper_32_bits(pci_addr),  in program_ib_windows()
496 	pcie->ib_wins_configured++;  in program_ib_windows()
502 static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,  in program_ob_windows()  argument
508 	if (win_num >= pcie->apio_wins) {  in program_ob_windows()
509 		dev_err(&pcie->pdev->dev,  in program_ob_windows()
518 	value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));  in program_ob_windows()
522 	csr_writel(pcie, value, PAB_AXI_AMAP_CTRL(win_num));  in program_ob_windows()
524 	csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num));  in program_ob_windows()
530 	csr_writel(pcie, lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK),  in program_ob_windows()
532 	csr_writel(pcie, upper_32_bits(cpu_addr),  in program_ob_windows()
535 	csr_writel(pcie, lower_32_bits(pci_addr),  in program_ob_windows()
537 	csr_writel(pcie, upper_32_bits(pci_addr),  in program_ob_windows()
540 	pcie->ob_wins_configured++;  in program_ob_windows()
543 static int mobiveil_bringup_link(struct mobiveil_pcie *pcie)  in mobiveil_bringup_link()  argument
549 		if (mobiveil_pcie_link_up(pcie))  in mobiveil_bringup_link()
555 	dev_err(&pcie->pdev->dev, "link never came up\n");  in mobiveil_bringup_link()
560 static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)  in mobiveil_pcie_enable_msi()  argument
562 	phys_addr_t msg_addr = pcie->pcie_reg_base;  in mobiveil_pcie_enable_msi()
563 	struct mobiveil_msi *msi = &pcie->msi;  in mobiveil_pcie_enable_msi()
565 	pcie->msi.num_of_vectors = PCI_NUM_MSI;  in mobiveil_pcie_enable_msi()
569 		       pcie->apb_csr_base + MSI_BASE_LO_OFFSET);  in mobiveil_pcie_enable_msi()
571 		       pcie->apb_csr_base + MSI_BASE_HI_OFFSET);  in mobiveil_pcie_enable_msi()
572 	writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);  in mobiveil_pcie_enable_msi()
573 	writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);  in mobiveil_pcie_enable_msi()
576 static int mobiveil_host_init(struct mobiveil_pcie *pcie)  in mobiveil_host_init()  argument
582 	value = csr_readl(pcie, PCI_PRIMARY_BUS);  in mobiveil_host_init()
585 	csr_writel(pcie, value, PCI_PRIMARY_BUS);  in mobiveil_host_init()
591 	value = csr_readl(pcie, PCI_COMMAND);  in mobiveil_host_init()
593 	csr_writel(pcie, value, PCI_COMMAND);  in mobiveil_host_init()
599 	pab_ctrl = csr_readl(pcie, PAB_CTRL);  in mobiveil_host_init()
601 	csr_writel(pcie, pab_ctrl, PAB_CTRL);  in mobiveil_host_init()
603 	csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),  in mobiveil_host_init()
610 	value = csr_readl(pcie, PAB_AXI_PIO_CTRL);  in mobiveil_host_init()
612 	csr_writel(pcie, value, PAB_AXI_PIO_CTRL);  in mobiveil_host_init()
615 	value = csr_readl(pcie, PAB_PEX_PIO_CTRL);  in mobiveil_host_init()
617 	csr_writel(pcie, value, PAB_PEX_PIO_CTRL);  in mobiveil_host_init()
627 	program_ob_windows(pcie, WIN_NUM_0, pcie->ob_io_res->start, 0,  in mobiveil_host_init()
628 			   CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res));  in mobiveil_host_init()
631 	program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);  in mobiveil_host_init()
634 	resource_list_for_each_entry(win, &pcie->resources) {  in mobiveil_host_init()
643 		program_ob_windows(pcie, pcie->ob_wins_configured,  in mobiveil_host_init()
650 	value = csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);  in mobiveil_host_init()
653 	csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);  in mobiveil_host_init()
656 	mobiveil_pcie_enable_msi(pcie);  in mobiveil_host_init()
664 	struct mobiveil_pcie *pcie;  in mobiveil_mask_intx_irq()  local
668 	pcie = irq_desc_get_chip_data(desc);  in mobiveil_mask_intx_irq()
670 	raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);  in mobiveil_mask_intx_irq()
671 	shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);  in mobiveil_mask_intx_irq()
673 	csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);  in mobiveil_mask_intx_irq()
674 	raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);  in mobiveil_mask_intx_irq()
680 	struct mobiveil_pcie *pcie;  in mobiveil_unmask_intx_irq()  local
684 	pcie = irq_desc_get_chip_data(desc);  in mobiveil_unmask_intx_irq()
686 	raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);  in mobiveil_unmask_intx_irq()
687 	shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);  in mobiveil_unmask_intx_irq()
689 	csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);  in mobiveil_unmask_intx_irq()
690 	raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);  in mobiveil_unmask_intx_irq()
730 	struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);  in mobiveil_compose_msi_msg()  local
731 	phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int));  in mobiveil_compose_msi_msg()
737 	dev_dbg(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n",  in mobiveil_compose_msi_msg()
757 	struct mobiveil_pcie *pcie = domain->host_data;  in mobiveil_irq_msi_domain_alloc()  local
758 	struct mobiveil_msi *msi = &pcie->msi;  in mobiveil_irq_msi_domain_alloc()
784 	struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d);  in mobiveil_irq_msi_domain_free()  local
785 	struct mobiveil_msi *msi = &pcie->msi;  in mobiveil_irq_msi_domain_free()
790 		dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n",  in mobiveil_irq_msi_domain_free()
802 static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie)  in mobiveil_allocate_msi_domains()  argument
804 	struct device *dev = &pcie->pdev->dev;  in mobiveil_allocate_msi_domains()
806 	struct mobiveil_msi *msi = &pcie->msi;  in mobiveil_allocate_msi_domains()
808 	mutex_init(&pcie->msi.lock);  in mobiveil_allocate_msi_domains()
810 						&msi_domain_ops, pcie);  in mobiveil_allocate_msi_domains()
828 static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)  in mobiveil_pcie_init_irq_domain()  argument
830 	struct device *dev = &pcie->pdev->dev;  in mobiveil_pcie_init_irq_domain()
835 	pcie->intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX,  in mobiveil_pcie_init_irq_domain()
836 						  &intx_domain_ops, pcie);  in mobiveil_pcie_init_irq_domain()
838 	if (!pcie->intx_domain) {  in mobiveil_pcie_init_irq_domain()
843 	raw_spin_lock_init(&pcie->intx_mask_lock);  in mobiveil_pcie_init_irq_domain()
846 	ret = mobiveil_allocate_msi_domains(pcie);  in mobiveil_pcie_init_irq_domain()
855 	struct mobiveil_pcie *pcie;  in mobiveil_pcie_probe()  local
864 	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));  in mobiveil_pcie_probe()
868 	pcie = pci_host_bridge_priv(bridge);  in mobiveil_pcie_probe()
870 	pcie->pdev = pdev;  in mobiveil_pcie_probe()
872 	ret = mobiveil_pcie_parse_dt(pcie);  in mobiveil_pcie_probe()
878 	INIT_LIST_HEAD(&pcie->resources);  in mobiveil_pcie_probe()
882 						    &pcie->resources, &iobase);  in mobiveil_pcie_probe()
892 	ret = mobiveil_host_init(pcie);  in mobiveil_pcie_probe()
899 	ret = mobiveil_pcie_init_irq_domain(pcie);  in mobiveil_pcie_probe()
905 	irq_set_chained_handler_and_data(pcie->irq, mobiveil_pcie_isr, pcie);  in mobiveil_pcie_probe()
907 	ret = devm_request_pci_bus_resources(dev, &pcie->resources);  in mobiveil_pcie_probe()
912 	list_splice_init(&pcie->resources, &bridge->windows);  in mobiveil_pcie_probe()
914 	bridge->sysdata = pcie;  in mobiveil_pcie_probe()
915 	bridge->busnr = pcie->root_bus_nr;  in mobiveil_pcie_probe()
920 	ret = mobiveil_bringup_link(pcie);  in mobiveil_pcie_probe()
940 	pci_free_resource_list(&pcie->resources);  in mobiveil_pcie_probe()