86 #define ECR_WRITE(p, v) frob_econtrol((p), 0xff, (v))  macro
192 		ECR_WRITE(p, oecr);  in change_mode()
198 	ECR_WRITE(p, oecr);  in change_mode()
262 		ECR_WRITE(p, s->u.pc.ecr);  in parport_pc_restore_state()
512 			ECR_WRITE(port, ecrval & ~(1<<2));  in parport_pc_fifo_write_block_pio()
1512 	ECR_WRITE(pb, 0x34);  in parport_ECR_present()
1592 	ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */  in parport_ECP_supported()
1593 	ECR_WRITE(pb, ECR_TST << 5); /* TEST FIFO */  in parport_ECP_supported()
1602 		ECR_WRITE(pb, ECR_SPP << 5);  in parport_ECP_supported()
1653 	ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */  in parport_ECP_supported()
1654 	ECR_WRITE(pb, 0xf4); /* Configuration mode */  in parport_ECP_supported()
1717 			ECR_WRITE(pb, i);  in intel_bug_present_check_epp()
1725 		ECR_WRITE(pb, ecr);  in intel_bug_present_check_epp()
1756 	ECR_WRITE(pb, ECR_PS2 << 5);  in parport_ECPPS2_supported()
1758 	ECR_WRITE(pb, oecr);  in parport_ECPPS2_supported()
1809 	ECR_WRITE(pb, 0x80);  in parport_ECPEPP_supported()
1813 	ECR_WRITE(pb, oecr);  in parport_ECPEPP_supported()
1864 	ECR_WRITE(pb, ECR_CNF << 5); /* Configuration MODE */  in programmable_irq_support()
1869 	ECR_WRITE(pb, oecr);  in programmable_irq_support()
1880 	ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */  in irq_probe_ECP()
1881 	ECR_WRITE(pb, (ECR_TST << 5) | 0x04);  in irq_probe_ECP()
1882 	ECR_WRITE(pb, ECR_TST << 5);  in irq_probe_ECP()
1889 	ECR_WRITE(pb, ECR_SPP << 5);  in irq_probe_ECP()
1930 		ECR_WRITE(pb, oecr);  in irq_probe_EPP()
2000 	ECR_WRITE(p, oecr);  in programmable_dma_support()
2237 		ECR_WRITE(p, 0x34);  in parport_pc_probe_port()